| Survey on routing algorithms in opportunistic networks B Poonguzharselvi, V Vetriselvi 2013 International Conference on Computer Communication and Informatics, 1-5, 2013 | 55 | 2013 |
| Trust framework for data forwarding in opportunistic networks using mobile traces B Poonguzharselvi, V Vetriselvi International Journal of Wireless & Mobile Networks 4 (6), 115, 2012 | 16 | 2012 |
| Data forwarding in opportunistic network using mobile traces B Poonguzharselvi, V Vetriselvi International Conference on Information Technology Convergence and Services …, 2012 | 9 | 2012 |
| Prediction of liver disease using machine learning algorithm and genetic algorithm B Poonguzharselvi, MMA Ashraf, VVSS Subhash, S Karunakaran Annals of the Romanian Society for Cell Biology, 2347–2357-2347–2357, 2021 | 7 | 2021 |
| VLSI Architecture of an 8-bit multiplier using Vedic mathematics in 180nm technology S Karunakaran, B Poonguzharselvi International Journal of Advances in Engineering & Technology 10 (3), 401, 2017 | 4 | 2017 |
| Exploration on Power Delay Product of Basic Logic Gates for Various CMOS Logic Styles S Karunakaran, B Poonguzharselvi Int. J. Eng. Stud 9, 0975-6469, 2017 | 2 | 2017 |
| Power Efficient VLSI Architecture of 4X4 Modified Column Bypassing Multiplier S Karunakaran, B Poonguzharselvi, T Logeswaran Annals of the Romanian Society for Cell Biology, 2116–2122-2116–2122, 2021 | 1 | 2021 |
| Exploration on Power Delay Product of various VLSI Multiplier Architectures S Karunakaran, Y Pandurangaiah, JA Prathap, B Poonguzharselvi International Journal of Mechanical Engineering and Technology 9 (1), 2018 | 1 | 2018 |
| Review on Placement Prediction Models B Poonguzharselvi Journal of Interdisciplinary Cycle Research 13 (5), 2259-2264, 2021 | | 2021 |
| High Performance VLSI Architecture for Braun multiplier BP S.Karunakaran International Journal of Innovative Technology and Exploring Engineering 8 …, 2019 | | 2019 |
| Investigations on power dissipation of low power VLSI architectures for Voltage level shifters BP S.Karunakaran Journal of Advanced Research in Dynamical and Control Systems 11 (5), 2229-2234, 2019 | | 2019 |
| Exploration of power delay product [PDP] on feedback based dual edge triggered flip flop utilizing dual sleep and dual slack approach JK Karunakaran S, Harshitha B, Poonguzharselvi B International Journal of Engineering and Technology 7 (7), 3388-3391, 2018 | | 2018 |
| Analysis of Low Power VLSI Design of Adder Cells BPMN S. Karunakaran Journal of Advanced Research in Dynamical & Control Systems, 883-887, 2018 | | 2018 |
