| Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance A Kundu, A Dasgupta, R Das, S Chakraborty, A Dutta, CK Sarkar Superlattices and Microstructures 94, 60-73, 2016 | 42 | 2016 |
| Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture R Das, S Chakraborty, A Dasgupta, A Dutta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 386-396, 2016 | 14 | 2016 |
| Comparisons between dual and tri material gate on a 32 nm double gate MOSFET A Dasgupta, R Das, S Chakraborty, A Dutta, A Kundu, CK Sarkar Nano 11 (10), 1650117, 2016 | 11 | 2016 |
| Impact of lateral straggle on the analog/RF performance of asymmetric gate stack double gate MOSFET GS Sivaram, S Chakraborty, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 477-488, 2016 | 8 | 2016 |
| A linearity based comparison between symmetric and asymmetric lateral diffusion for a 22 nm Underlapped DG-MOSFET A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 107, 69-82, 2017 | 6 | 2017 |
| An optimisation based study of underlap architecture of sub 16 nm double gate MOSFET for enhanced analog performance R Das, P Pandit, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar Materials Focus 6 (3), 305-309, 2017 | 6 | 2017 |
| Effect of spacer dielectric engineering on asymmetric source underlapped double gate MOSFET using gate stack A Chattopadhyay, A Dasgupta, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 101, 87-95, 2017 | 5 | 2017 |
| Monolithically integrated self-aligned SiN edge coupler with< 0.6/0.8 dB TE/TM insertion loss,<-39 dB back reflection and> 520 mW high-power handling capability Y Bian, T Hirokawa, V Karra, A Dasgupta, WS Lee, A Aboketaf, F Afzal, ... Optical Fiber Communication Conference, M3C. 3, 2023 | 4 | 2023 |
| Effect of channel engineering on analog/RF performance of underlapped gatestack DG-MOSFET in Sub-20nm regime A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar 2017 Devices for Integrated Circuit (DevIC), 299-302, 2017 | 4 | 2017 |
| An RF Based Optimization of Underlap of Sub 16 nm Double Gate MOSFET P Pandit, R Das, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar Advances in Industrial Engineering and Management 6 (1), 6-10, 2017 | 3 | 2017 |
| A comparative study of analog/RF performance: symmetric and asymmetric underlap gate stack DG-MOSFETs A Dasgupta, R Das, A Dutta, A Kundu, CK Sarkar 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 3 | 2016 |
| Reliability analysis through linearity and harmonic distortion of a dual-material-gate asymmetric underlapped DGMOSFET R Das, A Dasgupta, A Kundu Microelectronics Reliability 92, 106-113, 2019 | 2 | 2019 |
| Impact of asymmetric dual-k spacer in the underlap regions of sub 20 nm NMOSFET with gate stack S Chakraborty, A Dasgupta, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 98, 448-457, 2016 | 2 | 2016 |
| Antenna on Silicon Interconnect Fabric A Dasgupta, A Alam, G Ouyang, SC Jangam, SS Iyer 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 1788-1794, 2020 | 1 | 2020 |
| Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach S Chakraborty, A Dasgupta, R Das, M Kar, A Kundu, CK Sarkar Journal of Semiconductors 38 (12), 124001, 2017 | 1 | 2017 |
| Network on interconnect fabric and integrated antenna B Vaisband, SS Iyer, AA Bajwa, A Dasgupta, A Alam US Patent 11,239,542, 2022 | | 2022 |
| An Extensive Study on Different Underlap Architectures for Improved Analog/RF Performance of 32 nm DG-MOSFET A Singh, A Dasgupta, R Das, A Kundu, S Chaudhury | | |
| OPTIMISATION OF UNDERLAP OF SUB 16 nm DOUBLE GATE MOSFET FOR SUPERIOR ANALOG/RF PERFORMANCE R Das, P Pandit, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar BOOK OF, 85, 0 | | |
Atanu KunduHeritage Institute of TechnologyVerified email at heritageit.edu
