| Analog and RF performance evaluation of negative capacitance SOI junctionless transistor S Moparthi, KP Adarsh, PK Tiwari, GK Saramekala AEU-International Journal of Electronics and Communications 122, 153243, 2020 | 12 | 2020 |
| Investigation of temperature and source/drain overlap impact on negative capacitance silicon nanotube FET (NC Si NTFET) with sub-60mV/decade switching S Moparthi, PK Tiwari, VR Samoju, GK Saramekala IEEE Transactions on Nanotechnology 19, 800-806, 2020 | 9 | 2020 |
| Sensitivity analysis of silicon nanotube FET (Si NTFET) with TCAD assisted machine learning S Moparthi, PK Tiwari, GK Saramekala Silicon 14 (14), 9021-9031, 2022 | 5 | 2022 |
| Genetic algorithm-based threshold voltage prediction of SOI JLT using multi-variable nonlinear regression S Moparthi, PK Tiwari, GK Saramekala 2021 International Symposium on Devices, Circuits and Systems (ISDCS), 1-4, 2021 | 4 | 2021 |
| Machine learning based device simulation using multi-variable non-linear regression to assess the impact of device parameter variability on threshold voltage of double gate-all … S Moparthi, C Yadav, GK Saramekala, PK Tiwari 2020 IEEE 2nd International Conference on Circuits and Systems (ICCS), 64-67, 2020 | 4 | 2020 |
| Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO2|La2O3|HfO2 (HLH) Sandwich Gate … L Ramesh, S Moparthi, PK Tiwari, VR Samoju, GK Saramekala Semiconductors 54, 1290-1295, 2020 | 3 | 2020 |
| Temperature dependence of subthreshold characteristics of negative capacitance recessed-source/drain (NC RS/D) SOI MOSFET S Moparthi, PK Tiwari, VR Samoju, GK Saramekala 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 3 | 2019 |
| Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off S Moparthi, PK Tiwari, GK Saramekala Journal of Computational Electronics 22 (1), 250-259, 2023 | 1 | 2023 |
| Impact of drain voltage coupling on device and circuit-level performance of negative capacitance silicon nanotube FET S Moparthi, PK Tiwari, GK Saramekala IEEE Transactions on Nanotechnology 21, 547-554, 2022 | 1 | 2022 |
| Investigation of Subthreshold Characteristics of Negative Capacitance Single-Active Layer Double-Gate (NC-SALDG) Thin-Film Transistor (TFT) S Moparthi, R Lavudi, SR Suddapalli, GK Saramekala Silicon 14 (3), 1309-1314, 2022 | 1 | 2022 |
| Communications (AEÜ) S Moparthi, KP Adarsh, PK Tiwari, GK Saramekala | | 2020 |
| Device And Circuit Level Performance Analysis Of Negative Capacitance Silicon Nanotube Nc Sint Fets For Low Power Logic S Moparthi Calicut, 0 | | |
Dr. Gopi Krishna SaramekalaNational Institute of Technology CalicutVerified email at nitc.ac.in
