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Basavaraj Talawar
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Cited by
Year
Machine learning based framework to predict performance evaluation of on-chip networks
A Kumar, B Talawar
2018 Eleventh International Conference on Contemporary Computing (IC3), 1-6, 2018
122018
YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAs
P Prasad, K Parane, B Talawar
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
102018
Traffic engineered NoC for streaming applications
B Talwar, B Amrutur
Microprocessors and Microsystems 37 (3), 333-344, 2013
102013
Latency, power and performance trade-offs in network-on-chips by link microarchitecture exploration
B Talwar, S Kulkarni, B Amrutur
2009 22nd International Conference on VLSI Design, 163-168, 2009
92009
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images
AHK Upadhya, B Talawar, J Rajan
Journal of Real-Time Image Processing, 1-12, 2016
82016
A System-C based microarchitectural exploration framework for latency, power and performance trade-offs of on-chip Interconnection Networks
B Talwar, B Amrutur
Network on Chip Architectures, 30, 2008
82008
A method for resource and service discovery in MANETs
B Talwar, P Venkataram, LM Patnaik
Wireless Personal Communications 41 (2), 301-323, 2007
82007
Power and performance analysis of 3D network-on-chip architectures
B Halavar, B Talawar
Computers & Electrical Engineering 83, 106592, 2020
72020
FPGA based noc simulation acceleration framework supporting adaptive routing
K Parane, P Prabhu, B Talawar
2018 IEEE International Conference on Electronics, Computing and …, 2018
72018
Parallel iterative hill climbing algorithm to solve TSP on GPU
P Yelmewad, B Talawar
Concurrency and Computation: Practice and Experience 31 (7), e4974, 2019
62019
LBNoC: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
K Parane, B Talawar
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2020
52020
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
BMP Prasad, K Parane, B Talawar
2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019
52019
Design of an adaptive and reliable network on chip router architecture using FPGA
K Parane, BMP Prasad, B Talawar
2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019
42019
Floorplan Based Performance Estimation of Network-on-Chips using Regression Techniques
A Kumar, B Talawar
2019 IEEE 5th International Conference for Convergence in Technology (I2CT), 1-6, 2019
42019
High-performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs
P Prasad, K Parane, B Talawar
20th international symposium on quality electronic design (ISQED), 163-169, 2019
42019
Near optimal solution for traveling salesman problem using GPU
P Yelmewad, B Talawar
2018 IEEE International Conference on Electronics, Computing and …, 2018
42018
Accurate performance analysis of 3d mesh network on chip architectures
B Halavar, B Talawar
2018 IEEE International Conference on Electronics, Computing and …, 2018
42018
On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA processors in Gem5 Full System Simulator
B Vikas, B Talawar
2014 3rd International Conference on Eco-friendly Computing and …, 2014
42014
Parallel deterministic local search heuristic for minimum latency problem
P Yelmewad, B Talawar
Cluster Computing 24 (2), 969-995, 2021
32021
YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs
K Parane, BM Prabhu Prasad, B Talawar
Journal of Circuits, Systems and Computers 28 (12), 1950202, 2019
32019
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