Basavaraj Talawar

Cited by

	All	Since 2017
Citations	158	127
h-index	7	6
i10-index	3	2

200920102011201220132014201520162017201820192020202120222 2 2 6 3 1 6 7 3 4 19 37 38 26

Public access

View all

2 articles

3 articles

available

not available

Based on funding mandates

Co-authors

Khyamling ParaneNITKVerified email at nitk.edu.in
Prabhu Prasad B MAssistant Professor, IIIT DharwadVerified email at iiitdwd.ac.in
Pramod YelmewadResearch scholar, NITKVerified email at nitk.edu.in
Bheemappa HalavarFaculty of Computer Science and Engineering Indian Institute of Information Technology, SricityVerified email at iiits.in
Bharadwaj AmruturIndian Institute of ScienceVerified email at iisc.ac.in
venkataram pallapaprofessor of communication networks, Indian Institute of ScienceVerified email at ece.iisc.ernet.in
Ujjwal PasupuletyCisco Systems Private LimitedVerified email at cisco.com
ANIL KUMARAMITY University LucknowVerified email at lko.amity.edu
Shailesh KulkarniCTO, Tusk ICVerified email at tusk-ic.com
Lalit Mohan PatnaikAdjunct Professor and NASI(National Academy of Sciences India) Senior Scientist, NIAS,BangaloreVerified email at alumni.iisc.ac.in
Jeny RajanNational Institute of Technology Karnataka, IndiaVerified email at nitk.ac.in
Aditya K KamathUniversity of WashingtonVerified email at uw.edu
Keshavan VaradarajanIndian Institute of Science, BangaloreVerified email at acm.org
Mohit P. TahilianiAssistant Professor, Dept. of Computer Science and Engineering, NITK, SurathkalVerified email at nitk.edu.in
Pavan VachhaniStudent, National Institute of Technology KarnatakaVerified email at nitk.edu.in
Mishal ShahNational Institute of Technology Karnataka, SurathkalVerified email at nitk.edu.in
Mehnaz YunusVerified email at nitk.edu.in
Anil KumarDepartment of AIHCand Archaeology Visva Bharati, Santiniketan, IndiaVerified email at visva-bharati.ac.in

Basavaraj Talawar

Assistant Professor, National Institute of Technology Karnataka, Surathkal

Verified email at nitk.edu.in - Homepage

Computer Architecture High Performance Computing Simulation Acceleration


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Machine learning based framework to predict performance evaluation of on-chip networks A Kumar, B Talawar 2018 Eleventh International Conference on Contemporary Computing (IC3), 1-6, 2018	12	2018
YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAs P Prasad, K Parane, B Talawar 2018 31st International Conference on VLSI Design and 2018 17th …, 2018	10	2018
Traffic engineered NoC for streaming applications B Talwar, B Amrutur Microprocessors and Microsystems 37 (3), 333-344, 2013	10	2013
Latency, power and performance trade-offs in network-on-chips by link microarchitecture exploration B Talwar, S Kulkarni, B Amrutur 2009 22nd International Conference on VLSI Design, 163-168, 2009	9	2009
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images AHK Upadhya, B Talawar, J Rajan Journal of Real-Time Image Processing, 1-12, 2016	8	2016
A System-C based microarchitectural exploration framework for latency, power and performance trade-offs of on-chip Interconnection Networks B Talwar, B Amrutur Network on Chip Architectures, 30, 2008	8	2008
A method for resource and service discovery in MANETs B Talwar, P Venkataram, LM Patnaik Wireless Personal Communications 41 (2), 301-323, 2007	8	2007
Power and performance analysis of 3D network-on-chip architectures B Halavar, B Talawar Computers & Electrical Engineering 83, 106592, 2020	7	2020
FPGA based noc simulation acceleration framework supporting adaptive routing K Parane, P Prabhu, B Talawar 2018 IEEE International Conference on Electronics, Computing and …, 2018	7	2018
Parallel iterative hill climbing algorithm to solve TSP on GPU P Yelmewad, B Talawar Concurrency and Computation: Practice and Experience 31 (7), e4974, 2019	6	2019
LBNoC: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA K Parane, B Talawar ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2020	5	2020
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks BMP Prasad, K Parane, B Talawar 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019	5	2019
Design of an adaptive and reliable network on chip router architecture using FPGA K Parane, BMP Prasad, B Talawar 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019	4	2019
Floorplan Based Performance Estimation of Network-on-Chips using Regression Techniques A Kumar, B Talawar 2019 IEEE 5th International Conference for Convergence in Technology (I2CT), 1-6, 2019	4	2019
High-performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs P Prasad, K Parane, B Talawar 20th international symposium on quality electronic design (ISQED), 163-169, 2019	4	2019
Near optimal solution for traveling salesman problem using GPU P Yelmewad, B Talawar 2018 IEEE International Conference on Electronics, Computing and …, 2018	4	2018
Accurate performance analysis of 3d mesh network on chip architectures B Halavar, B Talawar 2018 IEEE International Conference on Electronics, Computing and …, 2018	4	2018
On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA processors in Gem5 Full System Simulator B Vikas, B Talawar 2014 3rd International Conference on Eco-friendly Computing and …, 2014	4	2014
Parallel deterministic local search heuristic for minimum latency problem P Yelmewad, B Talawar Cluster Computing 24 (2), 969-995, 2021	3	2021
YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs K Parane, BM Prabhu Prasad, B Talawar Journal of Circuits, Systems and Computers 28 (12), 1950202, 2019	3	2019

The system can't perform the operation now. Try again later.

Articles 1–20

Citations per year

Duplicate citations

Merged citations

Add co-authorsCo-authors

Follow

Cited by

Co-authors