P. Balasubramanian
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A fault tolerance improved majority voter for TMR system architectures
P Balasubramanian, K Prasad
WSEAS Transactions on Circuits and Systems 15, Article #14, 108-122, 2016
A delay efficient robust self-timed full adder
P Balasubramanian, DA Edwards
IEEE 3rd International Design and Test Workshop, 129-134, 2008
A robust asynchronous early output full adder
P Balasubramanian
WSEAS Transactions on Circuits and Systems 10 (7), 221-230, 2011
High speed gate level synchronous full adder designs
P Balasubramanian, NE Mastorakis
WSEAS Transactions on Circuits and Systems 8 (2), 290-300, 2009
A latency optimized biased implementation style weak-indication self-timed full adder
P Balasubramanian
Facta Universitatis, Series: Electronics and Energetics 28 (4), 657-671, 2015
RB_DSOP: A rule based disjoint sum of products synthesis method
P Balasubramanian, R Arisaka, HR Arabnia
12th International Conference on Computer Design, 39-43, 2012
Hardware Optimized and Error Reduced Approximate Adder
P Balasubramanian, DL Maskell
Electronics 8 (11), Article #1212, 1-15, 2019
Low power digital design using modified GDI method
P Balasubramanian, J John
IEEE International Conference on Design and Test of Integrated Systems in …, 2006
QDI decomposed DIMS method featuring homogeneous/heterogeneous data encoding
P Balasubramanian, NE Mastorakis
International Conference on Computers, Digital Communications and Computing …, 2011
A distributed minority and majority voting based redundancy scheme
P Balasubramanian, DL Maskell
Microelectronics Reliability 55 (9-10), 1373-1378, 2015
Self-timed realization of combinational logic
P Balasubramanian, DA Edwards
19th International Workshop on Logic and Synthesis (Co-sponsored by ACM …, 2010
Efficient realization of strongly indicating function blocks
P Balasubramanian, DA Edwards
IEEE Computer Society Annual Symposium on VLSI, 429-432, 2008
Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions
P Balasubramanian, N Mastorakis
Electronics 7 (12), Article #369, 1-12, 2018
A new design technique for weakly indicating function blocks
P Balasubramanian, DA Edwards
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008
Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders
P Balasubramanian, S Yamashita
SpringerPlus 5 (440 (1)), 1-26, 2016
Power, delay and area comparisons of majority voters relevant to TMR architectures
P Balasubramanian, NE Mastorakis
10th International Conference on Circuits, Systems, Signal and …, 2016
Self-timed section-carry based carry lookahead adders and the concept of alias logic
P Balasubramanian, DA Edwards, WB Toms
Journal of Circuits, Systems, and Computers 22 (4), 1350028-1 - 1350028-24, 2013
Comparative evaluation of quasi-delay-insensitive asynchronous adders corresponding to return-to-zero and return-to-one handshaking
P Balasubramanian
Facta Universitatis, Series: Electronics and Energetics (INVITED PAPER) 31 …, 2018
Self-timed logic and the design of self-timed adders
P Balasubramanian
The University of Manchester, 2010
An Approximate Adder with a Near-Normal Error Distribution: Design, Error Analysis and Practical Application
P Balasubramanian, R Nayar, DL Maskell, NE Mastorakis
IEEE Access 9, 4518-4530, 2021
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