| Dielectric resonator antenna for X band microwave application A Sharma, K Khare, SC Shrivastava Research & Reviews, International Journal of Advanced Research in Electrical …, 2016 | 169 | 2016 |
| Concept, design, and implementation of reconfigurable CORDIC S Aggarwal, PK Meher, K Khare IEEE transactions on very large scale integration (VLSI) systems 24 (4 …, 2015 | 77 | 2015 |
| Scale-free hyperbolic CORDIC processor and its application to waveform generation S Aggarwal, PK Meher, K Khare IEEE Transactions on Circuits and Systems I: Regular Papers 60 (2), 314-326, 2012 | 70 | 2012 |
| Area-time efficient scaling-free CORDIC using generalized micro-rotation selection S Aggarwal, PK Meher, K Khare IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011 | 69 | 2011 |
| Lector with footed-diode inverter: A technique for leakage reduction in domino circuits TK Gupta, K Khare Circuits, Systems, and Signal Processing 32, 2707-2722, 2013 | 41 | 2013 |
| High speed FPGA implementation of FIR filter for DSP applications R Thakur, K Khare International Journal of Modeling and Optimization 3 (1), 92-94, 2013 | 31 | 2013 |
| A novel approach for optimal design of sample rate conversion filter using linear optimization technique D Gautam, K Khare, BP Shrivastava IEEE Access 9, 44436-44441, 2021 | 28 | 2021 |
| Phase frequency detector of delay locked loop at high frequency K Khare, N Khare, P Deshpande, V Kulhade 2008 IEEE International Conference on Semiconductor Electronics, 113-116, 2008 | 27 | 2008 |
| Ultra-low power FinFET-based domino circuits AK Dadoria, K Khare, TK Gupta, RP Singh International Journal of Electronics 104 (6), 952-967, 2017 | 25 | 2017 |
| Designing of ultra‐low‐power high‐speed repeaters for performance optimization of VLSI interconnects at 32 nm A Khursheed, K Khare, FZ Haque International Journal of Numerical Modelling: Electronic Networks, Devices …, 2019 | 23 | 2019 |
| Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier K Khare, RP Singh, N Khare CSIR, 2006 | 23 | 2006 |
| Hardware efficient architecture for generating sine/cosine waves S Aggarwal, K Khare 2012 25th International Conference on VLSI Design, 57-61, 2012 | 22 | 2012 |
| VLSI design and analysis of low power 6T SRAM cell using cadence tool K Khare, N Khare, VK Kulhade, P Deshpande 2008 IEEE International Conference on Semiconductor Electronics, 117-121, 2008 | 22 | 2008 |
| Area and power efficient truncated booth multipliers using approximate carry-based error compensation Z Aizaz, K Khare IEEE Transactions on Circuits and Systems II: Express Briefs 69 (2), 579-583, 2021 | 20 | 2021 |
| Efficient FPGA Design and Implementation of Digital PID Controllers in Simulink® V Gupta, K Khare, RP Singh International Journal of Recent Trends in Engineering 2 (6), 147, 2009 | 19 | 2009 |
| Analysis of low voltage rail-to-rail CMOS operational amplifier design K Khare, N Khare, PK Sethiya 2008 International Conference on Electronic Design, 1-4, 2008 | 19 | 2008 |
| Efficient Design and FPGA Implementation of Digital Controller Using Xilinx SysGen® V Gupta, K Khare, RP Singh International Journal of Electronics Engineering 2 (1), 99-102, 2010 | 18 | 2010 |
| Designing high-performance thermally stable repeaters for nano-interconnects A Khursheed, K Khare, FZ Haque Journal of Computational Electronics 18 (1), 53-64, 2019 | 16 | 2019 |
| Fpga design and implementation issues of artificial neural network based pid controllers V Gupta, K Khare, RP Singh 2009 International Conference on Advances in Recent Technologies in …, 2009 | 16 | 2009 |
| A novel high-performance lekage-tolerant, wide fan-in domino logic circuit in deep-submicron technology A Dadoria, K Khare, TK Gupta, RP Singh Circuits and Systems 6 (04), 103, 2015 | 15 | 2015 |
tarun guptaAssistant Professor of Electronics and Communication Engineering, MANIT, BhopalVerified email at manit.ac.in
