| Accurus: A fast convergence technique for accuracy configurable approximate adder circuits V Benara, S Purini 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 577-582, 2016 | 17 | 2016 |
| RAG vs fine-tuning: Pipelines, tradeoffs, and a case study on agriculture A Balaguer, V Benara, RL de Freitas Cunha, RM Estevão Filho, T Hendry, ... arXiv e-prints, arXiv: 2401.08406, 2024 | 9 | 2024 |
| Bitwidth customization in image processing pipelines using interval analysis and SMT solvers S Purini, V Benara, Z Choudhury, U Bondhugula Proceedings of the 29th international conference on compiler construction …, 2020 | 4 | 2020 |
| NumS: Scalable Array Programming for the Cloud M Elibol, V Benara, S Yagati, L Zheng, A Cheung, MI Jordan, I Stoica arXiv preprint arXiv:2206.14276, 2022 | 2 | 2022 |
| Synthesizing power and area efficient image processing pipelines on fpgas using customized bit-widths V Benara, Z Choudhury, S Purini, U Bondhugula arXiv preprint arXiv:1803.02660, 2018 | 1 | 2018 |
| Crafting Interpretable Embeddings by Asking LLMs Questions V Benara, C Singh, JX Morris, R Antonello, I Stoica, AG Huth, J Gao arXiv preprint arXiv:2405.16714, 2024 | | 2024 |
