Sumit Ahuja
Sumit Ahuja
Research Scientist, Intel
Verified email at vt.edu
Title
Cited by
Cited by
Year
Power estimation methodology for a high-level synthesis framework
S Ahuja, DA Mathaikutty, G Singh, J Stetzer, SK Shukla, A Dingankar
2009 10th International Symposium on Quality Electronic Design, 541-546, 2009
352009
Model-driven test generation for system level validation
DA Mathaikutty, S Ahuja, A Dingankar, S Shukla
2007 IEEE International High Level Design Validation and Test Workshop, 83-90, 2007
322007
Hardware coprocessor synthesis from an ansi c specification
S Ahuja, ST Gurumani, C Spackman, SK Shukla
IEEE Design & Test of Computers 26 (4), 58-67, 2009
312009
High level power estimation models for FPGAs
A Lakshminarayana, S Ahuja, S Shukla
2011 IEEE Computer Society Annual Symposium on VLSI, 7-12, 2011
212011
MCBCG: Model checking based sequential clock-gating
S Ahuja, S Shukla
2009 IEEE International High Level Design Validation and Test Workshop, 20-25, 2009
202009
The model checking view to clock gating and operand isolation
J Brandt, K Schneider, S Ahuja, SK Shukla
2010 10th International Conference on Application of Concurrency to System …, 2010
17*2010
High level power estimation and reduction techniques for power aware hardware design
S Ahuja
Virginia Tech, 2010
172010
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
S Ahuja, A Lakshminarayana, SK Shukla
Springer Science & Business Media, 2011
152011
A methodology for power aware high-level synthesis of co-processors from software algorithms
S Ahuja, W Zhang, A Lakshminarayana, SK Shukla
2010 23rd International Conference on VLSI Design, 282-287, 2010
152010
Scope: Statistical regression based power models for co-processors power estimation
S Ahuja, DA Mathaikutty, A Lakshminarayana, SK Shukla
Journal of Low Power Electronics 5 (4), 407-415, 2009
142009
Applying verification collaterals for accurate power estimation
S Ahuja, DA Mathaikutty, S Shukla
2008 Ninth International Workshop on Microprocessor Test and Verification, 61-66, 2008
132008
Fault-and defect-tolerant architectures for nanocomputing
S Ahuja, G Singh, D Bhaduri, S Shukla
Bio-Inspired and Nanoscale Integrated Computing 1, 263, 2009
122009
Assertion-based modal power estimation
S Ahuja, DA Mathaikutty, S Shukla, A Dingankar
2007 Eighth International Workshop on Microprocessor Test and Verification, 3-7, 2007
122007
Field programmable gate arrays based overcurrent relays
S Ahuja, SK Balasubramanian
Electric Power Components and Systems 32 (3), 247-255, 2004
122004
Accurate power estimation of hardware co-processors using system level simulation
S Ahuja, DA Mathaikutty, A Lakshminarayana, S Shukla
2009 IEEE International SOC Conference (SOCC), 399-402, 2009
112009
System level simulation guided approach to improve the efficacy of clock-gating
S Ahuja, W Zhang, SK Shukla
2010 IEEE International High Level Design Validation and Test Workshop …, 2010
102010
Techniques for Power-aware Hardware Synthesis from Concurrent Action Oriented Specifications
G Singh, JB Schwartz, S Ahuja, SK Shukla
Journal of Low Power Electronics 3 (2), 156-166, 2007
72007
Posterior spinal dysraphism with lumbocostovertebral syndrome
G Singh, S Ahuja, R Kumar, A Chandra, B Ojha, C Singh, S Gupta
British Journal of neurosurgery 24 (2), 216-218, 2010
62010
Coprocessor design space exploration using high level synthesis
A Lakshminarayana, S Ahuja, S Shukla
2010 11th International Symposium on Quality Electronic Design (ISQED), 879-884, 2010
62010
Statistical regression based power models for co-processors for faster and accurate power estimation
S Ahuja, DA Mathaikutty, A Lakshminarayana, S Shukla
22nd IEEE International SOC Conference, 399-402, 2009
62009
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