Debabrata Mohapatra
Debabrata Mohapatra
ML Research Scientist, Reality Labs, Meta
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Cited by
Cited by
Low-power digital signal processing using approximate adders
V Gupta, D Mohapatra, A Raghunathan, K Roy
IEEE transactions on computer-aided design of integrated circuits and …, 2012
IMPACT: IMPrecise adders for low-power approximate computing
V Gupta, D Mohapatra, SP Park, A Raghunathan, K Roy
IEEE/ACM International Symposium on Low Power Electronics and Design, 409-414, 2011
Design of voltage-scalable meta-functions for approximate computing
D Mohapatra, VK Chippa, A Raghunathan, K Roy
2011 Design, Automation & Test in Europe, 1-6, 2011
Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency
VK Chippa, D Mohapatra, A Raghunathan, K Roy, ST Chakradhar
Proceedings of the 47th Design Automation Conference, 555-560, 2010
A priority-based 6T/8T hybrid SRAM architecture for aggressive voltage scaling in video applications
IJ Chang, D Mohapatra, K Roy
IEEE transactions on circuits and systems for video technology 21 (2), 101-112, 2011
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator
D Mohapatra, G Karakonstantis, K Roy
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
Scalable effort hardware design
VK Chippa, D Mohapatra, K Roy, ST Chakradhar, A Raghunathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (9 …, 2014
Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking
S Ghosh, D Mohapatra, G Karakonstantis, K Roy
IEEE transactions on very large scale integration (VLSI) systems 18 (9 …, 2009
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning
G Karakonstantis, D Mohapatra, K Roy
2009 IEEE Workshop on Signal Processing Systems, 133-138, 2009
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
D Mohapatra, G Karakonstantis, K Roy
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
Logic and memory design based on unequal error protection for voltage-scalable, robust and adaptive DSP systems
G Karakonstantis, D Mohapatra, K Roy
Journal of Signal Processing Systems 68, 415-431, 2012
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors
IJ Chang, D Mohapatra, K Roy
Proceedings of the 46th Annual Design Automation Conference, 670-675, 2009
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core
M Jung, T Song, Y Wan, YJ Lee, D Mohapatra, H Wang, G Taylor, ...
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013
Energy-efficient recognition and mining processor using scalable effort design
VK Chippa, H Jayakumar, D Mohapatra, K Roy, A Raghunathan
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013
Design considerations for edge neural network accelerators: An industry perspective
A Raha, SK Kim, DA Mathaikutty, G Venkataramanan, D Mohapatra, ...
2021 34th International Conference on VLSI Design and 2021 20th …, 2021
Schedule-aware tensor distribution module
G Chinya, H Liu, A Raha, D Mohapatra, C Brick, L Hacking
US Patent 11,907,827, 2024
Configurable processor element arrays for implementing convolutional neural networks
D Mohapatra, A Raha, G Chinya, H Liu, C Brick, L Hacking
US Patent App. 16/726,709, 2020
Approximate computing: Enabling voltage over-scaling in multimedia applications
D Mohapatra
Purdue University, 2011
Empirical evidence against CAPM: Relating alphas and returns to betas
M Agrawal, D Mohapatra, I Pollak
IEEE Journal of Selected Topics in Signal Processing 6 (4), 298-310, 2012
Special session: Approximate TinyML systems: Full system approximations for extreme energy-efficiency in intelligent edge devices
A Raha, S Ghosh, D Mohapatra, DA Mathaikutty, R Sung, C Brick, ...
2021 IEEE 39th International Conference on Computer Design (ICCD), 13-16, 2021
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