| Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET SM Biswal, B Baral, D De, A Sarkar Superlattices and Microstructures 91, 319-330, 2016 | 46 | 2016 |
| Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE SM Biswal, B Baral, D De, A Sarkar Superlattices and Microstructures 82, 103-112, 2015 | 28 | 2015 |
| An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects B Baral, AK Das, D De, A Sarkar International Journal of Numerical Modelling: Electronic Networks, Devices …, 2016 | 26 | 2016 |
| Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire (nw) Tunnel FET SM Biswal, B Baral, D De, A Sarkar Microsystem Technologies 25, 1855-1861, 2019 | 25 | 2019 |
| Effect of high-K spacer on the performance of non-uniformly doped DG-MOSFET SK Swain, SK Das, SM Biswal, S Adak, U Nanda, AA Sahoo, D Navak, ... 2019 Devices for Integrated Circuit (DevIC), 510-514, 2019 | 11 | 2019 |
| Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor B Baral, SM Biswal, D De, A Sarkar Simulation 93 (11), 985-993, 2017 | 11 | 2017 |
| Study of analog/Rf and stability investigation of surrounded gate junctionless graded channel MOSFET (SJLGC MOSFET) S Misra, SM Biswal, B Baral, SK Swain, SK Pati Silicon, 1-12, 2021 | 9 | 2021 |
| Effect of Gate Length Downscaling on RF/Analog and Linearity Performance of a Junctionless Double Gate MOSFET for Analog/Mixed Signal System-On-Chip Applications It’s … B Baral, SM Biswal, J Padhee, D De, A Sarkar Advances in Industrial Engineering and Management 5 (1), 130-137, 2016 | 4 | 2016 |
| Performance Analysis of Staggered Heterojunction based SRG TFET biosensor for health IoT application SM Biswal, SK Swain, B Baral, D Nayak, U Nanda, SK Das, D Tripthy 2019 Devices for Integrated Circuit (DevIC), 493-496, 2019 | 3 | 2019 |
| Effect of high-K spacer on the performance of gate-stack uniformly doped DG-MOSFET SK Das, SK Swain, SM Biswal, D Nayak, U Nanda, B Baral, D Tripathy 2019 Devices for Integrated Circuit (DevIC), 365-369, 2019 | 3 | 2019 |
| A novel driver less SRAM with indirect read for low energy consumption and read noise elimination D Nayak, U Nanda, PK Rout, SM Biswal, D Tripthy, SK Swain, B Baral, ... 2019 Devices for Integrated Circuit (DevIC), 314-317, 2019 | 3 | 2019 |
| Comparison of linearity performance of InAs based DG-MOSFETs with gate stack, SiO2 and HfO2 SK Swain, S Adak, SM Biswal, B Baral, S Parija 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 242-246, 2018 | 3 | 2018 |
| Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET B Baral, SM Biswal, D De, A Sarkar International Journal of Numerical Modelling: Electronic Networks, Devices …, 2017 | 3 | 2017 |
| Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry S Misra, SM Biswal, B Baral, SK Swain, A Sarkar, SK Pati Journal of Computational Electronics 20, 480-491, 2021 | 2 | 2021 |
| A Low Power LNA using Current Reused Technique for UWB Application D Tripathy, D Nayak, SM Biswal, SK Swain, B Baral, SK Das 2019 Devices for Integrated Circuit (DevIC), 310-313, 2019 | 2 | 2019 |
| Performance analysis of down scaling effect of Si based SRG tunnel FET SM Biswal, B Baral, SK Swain, SK Pati 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 344-348, 2018 | 2 | 2018 |
| Analog/radiofrequency and linearity performance of staggered heterojunction nanowire (nw) tunnel FET for low power application SM Biswal, B Baral, D De 2017 Devices for Integrated Circuit (DevIC), 441-445, 2017 | 2 | 2017 |
| Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET S Misra, SM Biswal, B Baral, SK Pati Transactions on Electrical and Electronic Materials 24 (4), 346-355, 2023 | 1 | 2023 |
| Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration SK Swain, SM Biswal, SK Das, S Adak, B Baral Nanoscience & Nanotechnology-Asia 10 (4), 419-424, 2020 | 1 | 2020 |
| Comparative Study of Gate Underlap and Overlap in Junction-less DG-MOSFETwith High k-Spacer through Simulation P Chand, N Agarwal, B Baral | 1 | 2015 |
Dr SUDHANSU MOHAN BISWALASSOCIATE PROF OF AEI DEPT.Silicon Institute of Technology,BhubaneswarVerified email at silicon.ac.in
