| Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits Nirmal Ch. Roy, Abhinav Gupta, Sanjeev Rai Microelectronics Journal 46 (10), 916–922, 2015 | 47 | 2015 |
| Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications Abhinav, S Rai Microelectronics Journal 64, 60–68, 2017 | 37 | 2017 |
| Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective MK Rai, A Gupta, S Rai Silicon, 2021 | 19 | 2021 |
| Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor A Kumar, A Gupta, S Rai AEU - International Journal of Electronics and Communications 95 (October …, 2018 | 18 | 2018 |
| A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs V Gupta, H Awasthi, N Kumar, AK Pandey, A Gupta Silicon, 2021 | 14 | 2021 |
| A Novel Approach to Investigate the Impact of Hetero-High-K Gate Stack on SiGe Junctionless Gate-All-Around (JL-GAA) MOSFET A Gupta, S Rai, N Kumar, D Sigroha, A Kishore, V Pathak, ZU Rahman Silicon, 2021 | 13 | 2021 |
| Impact of temperature variation on analog, hot-carrier injection and linearity parameters of nanotube junctionless double-gate-all-around (NJL-DGAA) MOSFETs N Kumar, H Awasthi, V Purwar, A Gupta, S Dubey Silicon 14 (6), 2679-2686, 2022 | 12 | 2022 |
| Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs A Kumar, TK Gupta, BP Shrivastava, A Gupta Microelectronics Journal 134, 105720, 2023 | 9 | 2023 |
| A novel approach to investigate analog and digital circuit applications of silicon Junctionless-Double-Gate (JL-DG) MOSFETs A Gupta, MK Rai, AK Pandey, D Pandey, S Rai Silicon 14 (13), 7577-7584, 2022 | 9 | 2022 |
| Keeper effect on nano scale silicon domino logic transistors AK Pandey, TK Gupta, A Gupta, D Pandey Silicon, 1-8, 2021 | 9 | 2021 |
| A study and comparative analysis of low power hybrid-CMOS 1-bit full adders in deep-submicron technology M Yadav, A Gupta, S Rai 4th International Conference on Power, Control & Embedded Systems (ICPCES), 1-7, 2017 | 6 | 2017 |
| A comparative study of junctionless dual material double gate silicon on insulator (SOI) and silicon on nothing (SON) MOSFET R Chauhan, Abhinav, A Kumar, S Rai 4th International Conference on Power, Control & Embedded Systems (ICPCES), 1-7, 2017 | 6 | 2017 |
| A Robust Design for Ultra Low Power Operation using Dynamic Threshold SCL Logic ABHINAV GUPTA, SANJEEV RAI, PROF.RAJEEV TRIPATHI 2nd International Conference on Computer and Communication Technology, 265 - 269, 2011 | 6* | 2011 |
| Temperature-dependent analytical modeling of graded-channel gate-all-around (GC-GAA) junctionless field-effect transistors (JLFETs) V Gupta, N Kumar, H Awasthi, S Rai, AK Pandey, A Gupta Journal of Electronic Materials 50, 3686-3691, 2021 | 5 | 2021 |
| An analysis of Si-tube based double-material double gate-all-around (DMDGAA) MOSFEts. ICE3.(2020) N Kumar, H Awasthi, V Purwar, A Gupta, A Gupta | 5 | 2020 |
| Potential Modeling of Oxide Engineered Doping-Less Dual-Material-Double-Gate Si–Ge MOSFET and Its Application A Gupta, A Singh, SK Gupta, SA Rai Journal of nanoelectronics and optoelectronics 13, 1115-1122, 2018 | 5 | 2018 |
| Impact of dielectric pocket on analog/RF performance of short channel double gate MOSFET A Gupta, N Maurya, S Rai 4th International Conference on Power, Control & Embedded Systems (ICPCES), 1-6, 2017 | 5 | 2017 |
| Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems A Kumar, TK Gupta, BP Shrivastava, A Gupta Microelectronics Journal 136, 105776, 2023 | 4 | 2023 |
| A novel technique to investigate the impact of temperature and process parameters on electrostatic and analog/RF performance of channel modulated junctionless gate-all-around … A Gupta, V Gupta, AK Pandey, TK Gupta Silicon 14 (16), 10613-10622, 2022 | 3 | 2022 |
| Modeling of Threshold Voltage and Subthreshold Current of Junctionless Channel-Modulated Dual-Material Double-Gate (JL-CM-DMDG) MOSFETs H Awasthi, V Purwar, A Gupta Silicon, 2021 | 3 | 2021 |
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