Follow
Henry Chin
Henry Chin
Verified email at sandisk.com
Title
Cited by
Cited by
Year
Three dimensional NAND device with silicide containing floating gates
H Chien, J Alsmeier, G Samachisa, H Chin, G Matamis, Y Zhang, J Kai, ...
US Patent 8,928,061, 2015
1602015
Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
N Mokhlesi, H Chin, D Zhao
US Patent 7,904,793, 2011
1452011
Soft bit data transmission for error correction control in non-volatile memory
N Mokhlesi, H Chin, D Zhao
US Patent 7,966,550, 2011
1192011
Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution
N Mokhlesi, H Chin
US Patent 7,957,187, 2011
1132011
Compensating for coupling during read operations in non-volatile storage
D Dutta, JW Lutze, Y Dong, H Chin, T Ishigaki
US Patent 7,876,611, 2011
1062011
Non-volatile memory with soft bit data transmission for error correction control
N Mokhlesi, H Chin, D Zhao
US Patent 7,966,546, 2011
782011
Metal control gate structures and air gap isolation in non-volatile memory
VR Purayath, T Pham, H Kinoshita, Y Zhang, H Chin, JK Kai, TW Orimoto, ...
US Patent 8,492,224, 2013
652013
Non-volatile memory with guided simulated annealing error correction control
H Chin, N Mokhlesi
US Patent 7,975,209, 2011
642011
Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution
N Mokhlesi, H Chin
US Patent 8,154,921, 2012
502012
Read scrub with adaptive counter management
Y Huang, C Avila, D Lee, H Chin, D Dutta, S Puthenthermadam, D Raghu
US Patent 9,552,171, 2017
432017
Three dimensional NAND device with silicide containing floating gates and method of making thereof
H Chien, J Alsmeier, G Samachisa, H Chin, G Matamis, Y Zhang, J Kai, ...
US Patent 9,165,940, 2015
412015
Adjusting resistance of non-volatile memory using dummy memory cells
H Chin, N Mokhlesi, D Zhao
US Patent 7,535,764, 2009
392009
Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation
GJ Hemink, SC Lee, A Khandelwal, H Chin, G Liang, D Lee
US Patent 8,526,233, 2013
362013
Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
N Mokhlesi, H Chin, D Zhao
US Patent 8,468,424, 2013
332013
Separate drain-side dummy word lines within a block to reduce program disturb
Z Zhang, H Chin, Y Dong
US Patent 10,297,330, 2019
312019
Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage
D Dutta, H Chin
US Patent 8,134,871, 2012
302012
Guided simulated annealing in non-volatile memory error correction control
H Chin, N Mokhlesi
US Patent 7,971,127, 2011
302011
Three dimensional NAND memory device with drain select gate electrode shared between multiple strings
V Diep, CH Lu, H Chin, C Chen
US Patent 10,566,059, 2020
252020
Synthesizer with reagent recycling
RN Zuckermann, K Truong, S DeRose-Juarez, KSC Kuey, MG Owings, ...
US Patent 6,033,631, 2000
252000
Partial block erase for open block reading in non-volatile memory
P Shukla, H Chin, D Lee, C Hsu
US Patent 9,552,885, 2017
242017
The system can't perform the operation now. Try again later.
Articles 1–20