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Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution N Mokhlesi, H Chin US Patent 7,957,187, 2011 | 113 | 2011 |
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Three dimensional NAND device with silicide containing floating gates and method of making thereof H Chien, J Alsmeier, G Samachisa, H Chin, G Matamis, Y Zhang, J Kai, ... US Patent 9,165,940, 2015 | 41 | 2015 |
Adjusting resistance of non-volatile memory using dummy memory cells H Chin, N Mokhlesi, D Zhao US Patent 7,535,764, 2009 | 39 | 2009 |
Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation GJ Hemink, SC Lee, A Khandelwal, H Chin, G Liang, D Lee US Patent 8,526,233, 2013 | 36 | 2013 |
Method for decoding data in non-volatile storage using reliability metrics based on multiple reads N Mokhlesi, H Chin, D Zhao US Patent 8,468,424, 2013 | 33 | 2013 |
Separate drain-side dummy word lines within a block to reduce program disturb Z Zhang, H Chin, Y Dong US Patent 10,297,330, 2019 | 31 | 2019 |
Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage D Dutta, H Chin US Patent 8,134,871, 2012 | 30 | 2012 |
Guided simulated annealing in non-volatile memory error correction control H Chin, N Mokhlesi US Patent 7,971,127, 2011 | 30 | 2011 |
Three dimensional NAND memory device with drain select gate electrode shared between multiple strings V Diep, CH Lu, H Chin, C Chen US Patent 10,566,059, 2020 | 25 | 2020 |
Synthesizer with reagent recycling RN Zuckermann, K Truong, S DeRose-Juarez, KSC Kuey, MG Owings, ... US Patent 6,033,631, 2000 | 25 | 2000 |
Partial block erase for open block reading in non-volatile memory P Shukla, H Chin, D Lee, C Hsu US Patent 9,552,885, 2017 | 24 | 2017 |