Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs S Yadav, N Chauhan, R Chawla, A Sharma, S Banchhor, R Pratap, ... Semiconductor Science and Technology 37 (8), 085023, 2022 | 1 | 2022 |
TSV induced stress model and its application in delay estimation R Chawla, S Yadav, A Sharma, B Kaur, R Pratap, B Anand 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 1 | 2018 |