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Raghav chawla
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Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure
A Sharma, N Alam, R Chawla, B Anand
2018 International Symposium on Devices, Circuits and Systems (ISDCS), 1-5, 2018
32018
Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs
S Yadav, N Chauhan, R Chawla, A Sharma, S Banchhor, R Pratap, ...
Semiconductor Science and Technology 37 (8), 085023, 2022
12022
TSV induced stress model and its application in delay estimation
R Chawla, S Yadav, A Sharma, B Kaur, R Pratap, B Anand
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
12018
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