| Multilevel Inverter: A Survey on Classical and Advanced Topologies, Control Schemes, Applications to Power System and Future Prospects S Choudhury, M Bajaj, T Dash, S Kamel, F Jurado Energies 14 (18), 5773, 2021 | 94 | 2021 |
| A novel control approach based on hybrid Fuzzy Logic and Seeker Optimization for optimal energy management between micro-sources and supercapacitor in an islanded Microgrid S Choudhury, TP Dash, P Bhowmik, PK Rout Journal of King Saud University-Engineering Sciences 32 (1), 27-41, 2020 | 57 | 2020 |
| Strain-Engineering in Nanowire Field-Effect Transistors at 3nm Technology Node TP Dash, S Dey, S Das, E Mohapatra, J Jena, CK Maiti Physica E: Low-dimensional Systems and Nanostructures 118, 113964, 2020 | 28 | 2020 |
| Study of strained-Si p-channel MOSFETs with HfO2 gate dielectric D Pradhan, S Das, TP Dash Superlattices and Microstructures 98, 203-207, 2016 | 21 | 2016 |
| Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes E Mohapatra, TP Dash, J Jena, S Das, CK Maiti SN Applied Sciences 3, 1-13, 2021 | 20 | 2021 |
| Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors E Mohapatra, TP Dash, J Jena, S Das, CK Maiti Physica Scripta 95 (6), 065808, 2020 | 20 | 2020 |
| Vertically-stacked silicon nanosheet field effect transistors at 3nm technology nodes TP Dash, S Dey, E Mohapatra, S Das, J Jena, CK Maiti 2019 Devices for Integrated Circuit (DevIC), 99-103, 2019 | 17 | 2019 |
| Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes S Dey, J Jena, E Mohapatra, TP Dash, S Das, CK Maiti Physica Scripta 95 (1), 014001, 2019 | 16 | 2019 |
| A comparative analysis of five level diode clamped and cascaded H-bridge multilevel inverter for harmonics reduction S Choudhury, S Nayak, TP Dash, PK Rout 2018 Technologies for Smart-City Energy Security and Power (ICSESP), 1-6, 2018 | 16 | 2018 |
| Modified brain storming optimization technique for transient stability improvement of SVC controller for a two machine system S Choudhury, T Dash World Journal of Engineering 18 (6), 841-850, 2021 | 15 | 2021 |
| Stress-induced variability studies in tri-gate FinFETs with source/drain stressor at 7 nm technology nodes TP Dash, J Jena, E Mohapatra, S Dey, S Das, CK Maiti Journal of Electronic Materials 48 (8), 5348-5362, 2019 | 15 | 2019 |
| Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node TP Dash, S Dey, S Das, J Jena, E Mohapatra, CK Maiti Journal of Micromechanics and Microengineering 29 (10), 104001, 2019 | 11 | 2019 |
| Improvement of performance and quality of power in grid tied SOFC through crow search optimization technique S Choudhury, B Sen, S Kumar, S Sahani, A Pattnaik, T Dash 2020 5th International Conference on Communication and Electronics Systems …, 2020 | 10 | 2020 |
| Performance and opportunities of gate-all-around vertically-stacked nanowire transistors at 3nm technology nodes S Dey, TP Dash, E Mohapatra, J Jena, S Das, CK Maiti 2019 Devices for Integrated Circuit (DevIC), 94-98, 2019 | 10 | 2019 |
| Electron mobility modeling in strained-Si n-MOSFETs using TCAD TP Dash, D Pradhan, S Das, RK Nanda 2016 IEEE Annual India Conference (INDICON), 1-4, 2016 | 10 | 2016 |
| Strain-engineering in AlGaN/GaN HEMTs: impact of silicon nitride passivation layer on electrical performance S Das, T Dash, D Jena, E Mohapatra, CK Maiti Physica Scripta, 2021 | 7 | 2021 |
| A robust modified harmony search evolutionary technique for transient stability enhancement in a two machine system through STATCOM S Choudhury, A Satpathy, P Rout, BK Prusty, S Bhakat, TP Dash 2019 IEEE International Conference on Electrical, Computer and Communication …, 2019 | 7 | 2019 |
| Experimental and simulation study of charge transport mechanism in HfTiOx high-k gate dielectric on SiGe heterolayers PP Maiti, A Dash, S Guhathakurata, S Das, A Bag, TP Dash, G Ahmad, ... Bulletin of Materials Science 45 (1), 39, 2022 | 6 | 2022 |
| Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs E Mohapatra, TP Dash, J Jena, S Das, CK Maiti 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 331-334, 2020 | 6 | 2020 |
| A supervisory state of charge and state of power management control strategy among hybrid energy storage systems through thermal exchange optimization technique S Choudhury, N Khandelwal, A Kumar, A Shukla, A Jha, M Mohanty, ... 2020 IEEE Calcutta Conference (CALCON), 323-327, 2020 | 6 | 2020 |
Dr. Jhansirani JenaAsst. Prof., Siksha 'O' Anusandhan (Deemed to be university)Verified email at soa.ac.in
