| Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET Y Choi, K Lee, KY Kim, S Kim, J Lee, R Lee, HM Kim, YS Song, S Kim, ... Solid-State Electronics 164, 107686, 2020 | 49 | 2020 |
| Design and optimization of triple-k spacer structure in two-stack nanosheet FET from OFF-state leakage perspective D Ryu, M Kim, S Kim, Y Choi, J Yu, JH Lee, BG Park IEEE Transactions on Electron Devices 67 (3), 1317-1322, 2020 | 28 | 2020 |
| Electrical and thermal performances of omega-shaped-gate nanowire field effect transistors for low power operation YS Song, S Hwang, KK Min, T Jang, Y Choi, J Yu, JH Lee, BG Park Journal of nanoscience and nanotechnology 20 (7), 4092-4096, 2020 | 25 | 2020 |
| Memory Designing Using Low-Power FETs for Future Technology Nodes YS Song, SB Rahi, CK Pandey, S Tayal, Y Choi, B Joseph, T Joshi, ... Emerging Low-Power Semiconductor Devices, 197-222, 2022 | | 2022 |
| 197 Memory Designing Using Low-Power FETs for Future Technology Nodes YS Song, SB Rahi, CK Pandey, S Tayal SR, Y Choi, B Joseph, T Joshi, ... Emerging Low-Power Semiconductor Devices: Applications for Future Technology …, 0 | | |
