Santanu Chattopadhyay
Santanu Chattopadhyay
Professor, Dept. of Electronics and Elec. Comm. Engg., Indian Institute of Technology, Kharagpur
Verified email at ece.iitkgp.ac.in
Title
Cited by
Cited by
Year
Additive cellular automata: theory and applications
PP Chaudhuri, DR Chowdhury, S Nandi, S Chattopadhyay
John Wiley & Sons, 1997
7041997
A survey on application mapping strategies for network-on-chip design
PK Sahu, S Chattopadhyay
Journal of systems architecture 59 (1), 60-76, 2013
3272013
Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization
PK Sahu, T Shah, K Manna, S Chattopadhyay
IEEE transactions on very large scale integration (VLSI) systems 22 (2), 300-312, 2013
1152013
CA and Its Applications: A Brief Survey
PP Chaudhuri, DR Chowdhury, S Nandi, S Chattopadhyay
Additive cellular automata-theory and applications 1, 6-25, 1997
951997
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier
S Chattopadhyay, S Adhikari, S Sengupta, M Pal
IEEE transactions on very large scale integration (VLSI) systems 8 (6), 724-735, 2000
872000
Network-on-chip: the next generation of system-on-chip integration
S Kundu, S Chattopadhyay
Taylor & Francis, 2014
652014
Genetic algorithm based approach for low power combinational circuit testing
S Chattopadhyay, N Choudhary
16th International Conference on VLSI Design, 2003. Proceedings., 552-557, 2003
512003
Application mapping onto mesh structured network-on-chip using particle swarm optimization
PK Sahu, P Venkatesh, S Gollapalli, S Chattopadhyay
2011 ieee computer society annual symposium on vlsi, 335-336, 2011
502011
Low power state assignment and flipflop selection for finite state machine synthesis-a genetic algorithmic approach
S Chattopadhyay
IEE Proceedings-Computers and Digital Techniques 148 (45), 147-151, 2001
492001
Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router
S Kundu, J Soumya, S Chattopadhyay
Microprocessors and Microsystems 36 (6), 471-488, 2012
412012
Cellular automata-based recursive pseudoexhaustive test pattern generator
P Dasgupta, S Chattopadhyay, PP Chaudhuri, I Sengupta
IEEE Transactions on Computers 50 (2), 177-185, 2001
412001
Finite state machine state assignment targeting low power consumption
S Chattopadhyay, PN Reddy
IEE Proceedings-Computers and Digital Techniques 151 (1), 61-70, 2004
372004
KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer
S Chattopadhyay, S Roy, PP Chaudhuri
IEEE transactions on computer-aided design of integrated circuits and …, 1997
361997
A new application mapping algorithm for mesh based network-on-chip design
PK Sahu, N Shah, K Manna, S Chattopadhyay
2010 Annual IEEE India Conference (INDICON), 1-4, 2010
342010
Area conscious state assignment with flip-flop and output polarity selection for finite state machine synthesis—a genetic algorithm approach
S Chattopadhyay
The Computer Journal 48 (4), 443-450, 2005
342005
Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip
PK Sahu, K Manna, N Shah, S Chattopadhyay
Journal of Systems Architecture 60 (7), 562-578, 2014
332014
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
S Kundu, S Chattopadhyay
International Journal of High Performance Systems Architecture 1 (3), 163-182, 2008
332008
Genetic algorithm based test scheduling and test access mechanism design for system-on-chips
S Chattopadhyay, KS Reddy
16th International Conference on VLSI Design, 2003. Proceedings., 341-346, 2003
332003
Synthesis of highly testable fixed-polarity AND-XOR canonical networks-A genetic algorithm-based approach
S Chattopadhyay, S Roy, PP Chaudhuri
IEEE transactions on computers 45 (4), 487-490, 1996
311996
Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machine synthesis
S Chattopadhyay, PP Chaudhuri
Proceedings Eleventh International Conference on VLSI Design, 522-527, 1998
301998
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