Santanu Chattopadhyay
Santanu Chattopadhyay
Professor, Dept. of Electronics and Elec. Comm. Engg., Indian Institute of Technology, Kharagpur
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Cited by
Cited by
Additive Cellular Automata: Theory and Applications, Volume 1
PP Chaudhuri, DR Chowdhury, S Nandi, S Chattopadhyay
John Wiley & Sons, 1997
A survey on application mapping strategies for network-on-chip design
PK Sahu, S Chattopadhyay
Journal of systems architecture 59 (1), 60-76, 2013
Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization
PK Sahu, T Shah, K Manna, S Chattopadhyay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (2), 300-312, 2013
CA and Its Applications: A Brief Survey
PP Chaudhuri, DR Chowdhury, S Nandi, S Chattopadhyay
Additive Cellular Automata-Theory and Applications 1, 6-25, 1997
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier
S Chattopadhyay, S Adhikari, S Sengupta, M Pal
IEEE transactions on very large scale integration (VLSI) systems 8 (6), 724-735, 2000
Network-on-chip: the next generation of system-on-chip integration
S Kundu, S Chattopadhyay
Taylor & Francis, 2014
Application mapping onto mesh structured network-on-chip using particle swarm optimization
PK Sahu, P Venkatesh, S Gollapalli, S Chattopadhyay
2011 ieee computer society annual symposium on vlsi, 335-336, 2011
Genetic algorithm based approach for low power combinational circuit testing
S Chattopadhyay, N Choudhary
16th International Conference on VLSI Design, 2003. Proceedings., 552-557, 2003
Low power state assignment and flipflop selection for finite state machine synthesis—A genetic algorithmic approach
S Chattopadhyay
IEE Proceedings-Computers and Digital Techniques 148 (4), 147-151, 2001
Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router
S Kundu, J Soumya, S Chattopadhyay
Microprocessors and Microsystems 36 (6), 471-488, 2012
Cellular automata-based recursive pseudoexhaustive test pattern generator
P Dasgupta, S Chattopadhyay, PP Chaudhuri, I Sengupta
IEEE Transactions on Computers 50 (2), 177-185, 2001
Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip
PK Sahu, K Manna, N Shah, S Chattopadhyay
Journal of Systems Architecture 60 (7), 562-578, 2014
Area conscious state assignment with flip-flop and output polarity selection for finite state machine synthesis—a genetic algorithm approach
S Chattopadhyay
The Computer Journal 48 (4), 443-450, 2005
Finite state machine state assignment targeting low power consumption
S Chattopadhyay, PN Reddy
IEE Proceedings-Computers and Digital Techniques 151 (1), 61-70, 2004
A new application mapping algorithm for mesh based network-on-chip design
PK Sahu, N Shah, K Manna, S Chattopadhyay
2010 Annual IEEE India Conference (INDICON), 1-4, 2010
Design and evaluation of ZMesh topology for on-chip interconnection networks
N Prasad, P Mukherjee, S Chattopadhyay, I Chakrabarti
Journal of Parallel and Distributed Computing 113, 17-36, 2018
Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform
N Chatterjee, S Paul, S Chattopadhyay
ACM Transactions on Embedded Computing Systems (TECS) 16 (4), 1-24, 2017
Genetic algorithm based test scheduling and test access mechanism design for system-on-chips
S Chattopadhyay, KS Reddy
16th International Conference on VLSI Design, 2003. Proceedings., 341-346, 2003
KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer
S Chattopadhyay, S Roy, PP Chaudhuri
IEEE transactions on computer-aided design of integrated circuits and …, 1997
A scan obfuscation guided design-for-security approach for sequential circuits
R Karmakar, S Chattopadhyay, R Kapur
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (3), 546-550, 2019
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