Follow
Julius Mandelblat
Julius Mandelblat
Verified email at intel.com
Title
Cited by
Cited by
Year
Inside 6th-generation intel core: New microarchitecture code-named skylake
J Doweck, WF Kao, AK Lu, J Mandelblat, A Rahatekar, L Rappoport, ...
IEEE Micro 37 (2), 52-62, 2017
2002017
Dynamic memory sizing for power reduction
J Mandelblat, M Mehalel, A Mendelson, A Naveh
US Patent App. 11/208,935, 2007
632007
CMP Implementation in Systems Based on the Intel Core Duo Processor.
A Mendelson, J Mandelblat, S Gochman, A Shemer, R Chabukswar, ...
Intel Technology Journal 10 (2), 2006
452006
Hybrid exclusive multi-level memory architecture with memory management
DG Feekes, S Raikin, B Fanning, J Ray, J Mandelblat, A Berkovits, ...
US Patent 9,734,079, 2017
362017
Selective prefetching for a sectored cache
AV Anantaraman, Z Greenfield, AV Nori, JY Mandelblat
US Patent 9,418,013, 2016
332016
Intel alder lake cpu architectures
E Rotem, A Yoaz, L Rappoport, SJ Robinson, JY Mandelblat, A Gihon, ...
IEEE Micro 42 (3), 13-19, 2022
242022
Reducing back invalidation transactions from a snoop filter
T Kurts, K Cheng, JD Gilbert, J Mandelblat
US Patent 8,015,365, 2011
222011
Technology insight: Intel’s next generation microarchitecture code name skylake
J Mandelblat
Intel Developer Forum, San Francisco, 2015
172015
Inside 6th gen Intel®Core™: New microarchitecture code named skylake
I Anati, D Blythe, J Doweck, H Jiang, W Kao, J Mandelblat, L Rappoport, ...
2016 IEEE Hot Chips 28 Symposium (HCS), 1-39, 2016
142016
Use of error correcting code to carry additional data bits
D Greenspan, A Rubinstein, JY Mandelblat
US Patent 9,559,726, 2017
92017
Apparatus and method for implement a multi-level memory hierarchy
T Yigzaw, O Lempel, H Shafi, GN Santhanakrishnan, JA Vargas, ...
US Patent 9,448,879, 2016
92016
Architecture for dynamic transformation of memory configuration
N Bonen, J Mandelblat, N Sucher
US Patent 10,877,693, 2020
82020
Device, system and method of multi-state cache coherence scheme
A Mendelson, J Mandelblat, C Hughes, D Kim, V Lee, A Nguyen, ...
US Patent App. 11/316,949, 2007
82007
Cache behavior for secure memory repartitioning systems
M Ozsoy, KC Zmudzinski, L Novakovsky, J Mandelblat, FX McKeen, ...
US Patent App. 15/721,631, 2019
72019
Performance monitoring in heterogeneous systems
A Yasin, J Mandelblat, E Weissmann, RA Chabukswar, MW Chynoweth
US Patent App. 16/729,370, 2021
62021
Apparatus and method for memory-hierarchy aware producer-consumer instruction
S Raikin, R Sade, R Valentine, JY Mandelblat, R Shalev, L Novakovsky
US Patent 9,990,287, 2018
52018
Cache allocation with code and data prioritization
AJ Herdrich, E Verplanke, R Iyer, CC Gianos, JD Chamberlain, R Singhal, ...
US Patent 9,563,564, 2017
52017
Device, system and method of managing a resource request
A Mendelson, J Mandelblat, L Novakovsky
US Patent 7,958,510, 2011
42011
Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
A Herdrich, E Verplanke, R Iyer, C Gianos, JD Chamberlain, R Singh, ...
US Patent App. 14/671,496, 2016
32016
Adaptive admission control for on die interconnect
G Satat, E Bolotin, J Mandelblat, J Gaur, S Majumder, RK Venkatesan
US Patent App. 14/142,748, 2015
32015
The system can't perform the operation now. Try again later.
Articles 1–20