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Neha Paras
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Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications
N Paras, SS Chauhan
Microelectronic Engineering 216, 111043, 2019
382019
Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs
N Paras, SS Chauhan
Applied Physics A 125 (5), 316, 2019
302019
A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications
N Paras, SS Chauhan
Microelectronic Engineering 217, 111103, 2019
292019
Simulation of mems based capacitive pressure sensor using comsol multiphysics
G Mishra, N Paras, A Arora, PJ George
International Journal of Applied Engineering Research 7 (11), 2012, 2012
262012
Design and integration of vertical TFET and memristor for better realization of logical functions
J Singh, S Singh, N Paras
Silicon 15 (2), 783-792, 2023
112023
Vertical tunneling based tunnel field effect transistor with workfunction engineered hetero-gate to enhance DC characteristics
N Paras, SS Chauhan
Journal of Nanoelectronics and Optoelectronics 14 (1), 50-53, 2019
112019
Impact of the self-heating effect on nanosheet field effect transistor performance
B Smaani, N Paras, SB Rahi, YS Song, R Yadav, S Tayal
ECS Journal of Solid State Science and Technology 12 (2), 021005, 2023
32023
Optimization of Design Parameters for Vertical Tunneling Based Dual Metal Dual Gate TFET
N Paras, SS Chauhan
2019 International Conference on Advances in Computing and Communication …, 2019
32019
Simulation of MEMS Capacitive Pressure Sensor Using Comsol Multhysics
M Gitesh, P Neha, A Arti, PJ George
International Journal of Applied Engineering Research 7 (11), 2012
22012
Performance Analysis of Tunnel Field Effect Transistor for Low‐Power Applications
D Kumar, SB Rahi, N Paras
Intelligent Green Technologies for Sustainable Smart Cities, 195-225, 2022
12022
Design and simulation of uncooled microbolometer using coventorware
S Arora, N Paras, A Gurjar, R Narwal, B Prasad, D Kumar
AIP Conference Proceedings 1724 (1), 2016
12016
Dynamic Power Reduction in dual edge triggered D-Flip-flop clock gating using Memristor
P Sharma, M Bharti, N Paras
2024 IEEE International Students' Conference on Electrical, Electronics and …, 2024
2024
Design and analysis of novel La: HfO2 gate stacked ferroelectric tunnel FET for non-volatile memory applications
N Paras, SB Rahi, AK Upadhyay, M Bharti, YS Song
Memories-Materials, Devices, Circuits and Systems, 100101, 2024
2024
Compact analytical model for graphene field effect transistor: Drift-diffusion approach
AK Upadhyay, SB Rahi, B Smaani, BMM Tripathi, N Paras, R Mathew, ...
Advanced MOS Devices and their Circuit Applications, 56-73, 2024
2024
Recent Challenges in the IT and Semiconductor Industry: From Von Neumann Architecture to the Future
YS Song, SB Rahi, N Bagga, S Rathore, RK Jaisawal, P Vimala, N Paras, ...
Negative Capacitance Field Effect Transistors, 1-10, 2023
2023
Designing of Nonvolatile Memories Utilizing Tunnel Field Effect Transistor
P Kumar, N Paras, M Bharti
Tunneling Field Effect Transistors, 235-250, 2023
2023
Analysis and Implementation of Approximate 4-2 Compressors for Approximate Multipliers
J Kokkiligadda, DK Jhariya, N Paras
2023 2nd International Conference on Paradigm Shifts in Communications …, 2023
2023
Investigation of the Direct Source to Drain Tunneling in 5 nm Nanotube Junctionless Field Effect Transistor
PK Gautam, M Bharti, N Paras
2023 2nd International Conference on Paradigm Shifts in Communications …, 2023
2023
Room temperature magento-electric coupling in Pb–Zn substituted Co2Y-hexaferrite
Deepika, N Paras, A Arya, R Kumar, S Sharma, S Lal, V Kumar, A Gaur
Journal of Materials Science: Materials in Electronics 33 (21), 16874-16888, 2022
2022
Linearity Analysis of Line Tunneling Based TFET for High-Performance RF Applications
N Paras, SS Chauhan
International Conference on Advanced Communication and Computational …, 2019
2019
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