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Koutaro Hachiya
Koutaro Hachiya
Teikyo Heisei University
Verified email at thu.ac.jp
Title
Cited by
Cited by
Year
On-chip thermal gradient analysis and temperature flattening for SoC design
T Sato, J Ichimiya, N Ono, K Hachiya, M Hashimoto
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
632005
On-Chip thermal gradient analysis and temperature flattening for SoC design
T Sato, J Ichimiya, N Ono, K Hachiya, M Hashimoto
Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC …, 2005
632005
Parallel iterative solvers for sparse linear systems in circuit simulation
A Basermann, U Jaekel, M Nordhausen, K Hachiya
Future Generation Computer Systems 21 (8), 1275-1284, 2005
302005
Parallel Iterative Solvers for Sparse Linear Systems in Circuit Simulation
A Basermann, U Jaekel, K Hachiya
Progress in Industrial Mathematics at ECMI 2002, 235-239, 2002
302002
Simulation device and its method for simulating operation of large-scale electronic circuit by parallel processing
K Hachiya
US Patent 6,144,932, 2000
272000
Method and apparatus for matrix reordering and electronic circuit simulation
K Hachiya
US Patent 7,089,159, 2006
142006
ESSENCE‐Q obtained in routine Japanese public child health check‐ups may be a valuable tool in neurodevelopmental screening
Y Hatakenaka, M Maeda, H Ninomiya, K Hachiya, E Fernell, C Gillberg
Acta Paediatrica 109 (4), 764-773, 2020
122020
Thermal placement on PCB of components including 3D ICs
Y Satomi, K Hachiya, T Kanamoto, R Watanabe, A Kurokawa
IEICE Electronics Express 17 (3), 20190737-20190737, 2020
112020
Symbolic calculation system, symbolic calculation method and parallel circuit simulation system
K Hachiya
US Patent 6,636,828, 2003
112003
Preconditioning parallel sparse iterative solvers for circuit simulation
A Basermann, U Jaekel, K Hachiya
Proceedings of the 8th SIAM Proceedings on Applied Linear Algebra …, 2003
112003
Circuit partitioning apparatus for executing parallel circuit simulation and method therefor
K Hachiya
US Patent 6,031,979, 2000
112000
Open defect detection of through silicon vias for structural power integrity test of 3D-ICs
K Hachiya, A Kurokawa
2019 IEEE 23rd workshop on signal and power integrity (SPI), 1-4, 2019
102019
Neural network-based 3D IC interconnect capacitance extraction
R Kasai, T Kanamoto, M Imai, A Kurokawa, K Hachiya
2019 2nd International Conference on Communication Engineering and …, 2019
92019
Variability Cancellation to Improve Diagnostic Performance of Testing Through Silicon Vias in Power Distribution Network of 3D-IC
K Hachiya, A Kurokawa
The IEEE International 3D Systems Integration Conference (3DIC 2019), 6, 2019
62019
Comparison of diagnostic performance metrics for test point selection in analog circuits
K Hachiya, A Kurokawa
The 22nd Workshop on Synthesis And System Integration of Mixed Information …, 2019
52019
Optimization of full-chip power distribution networks in 3D ICs
Y Satomi, K Hachiya, T Kanamoto, A Kurokawa
2018 IEEE 3rd International Conference on Integrated Circuits and …, 2018
52018
Impact of self-heating in wire interconnection on timing
T Kanamoto, T Okumura, K Furukawa, H Takafuji, A Kurokawa, K Hachiya, ...
IEICE transactions on electronics 93 (3), 388-392, 2010
52010
Newly collected late jurassic ammonites from Kurisaka, Tokushima Prefecture, Japan
T Sato, Y Tsujino, K Ishida, T Kozai, K Hachiya
Bulletin of the Tokushima Prefectural Museum 18, 1-20, 2008
52008
Parallel solution techniques for sparse linear systems in circuit simulation
A Basermann, F Cortial-Goutaudier, U Jaekel, K Hachiya
Scientific Computing in Electrical Engineering: Proceedings of the SCEE-2002 …, 2004
52004
Fast on-chip inductance extraction of VLSI including angled interconnects
A Kurokawa, K Hachiya, T Sato, K Tokumasu, H Masuda
IEICE transactions on fundamentals of electronics, communications and …, 2003
52003
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Articles 1–20