| A priori wirelength and interconnect estimation based on circuit characteristics S Balachandran, D Bhatia IEEE Transactions on computer-aided design of integrated circuits and …, 2005 | 41 | 2005 |
| Fast-SL: An efficient algorithm to identify synthetic lethal sets in metabolic networks A Pratapa, S Balachandran, K Raman Bioinformatics, 2015 | 30 | 2015 |
| The Implications of Shared Data Synchronization Techniques on Multi-core Energy Efficiency AJ Gautham, K Korgaonkar, S Pathanjali, S Balachandran, V Kamakoti Proceedings of the 2012 USENIX conference on Power-Aware Computing and …, 2012 | 29 | 2012 |
| On metrics for comparing routability estimation methods for FPGAs P Kannan, S Balachandran, D Bhatia Proceedings of the 39th annual Design Automation Conference, 70-75, 2002 | 28 | 2002 |
| fGREP-fast generic routing demand estimation for placed FPGA circuits PV Kannan, S Balachandran, D Bhatia International Conference on Field Programmable Logic and Applications, 37-47, 2001 | 20 | 2001 |
| A new parallel algorithm for minimum spanning tree problem R Setia, A Nedunchezhian, S Balachandran Proc. International Conference on High Performance Computing (HiPC), 1-5, 2009 | 18 | 2009 |
| A new wirelength model for analytical placement BNB Ray, S Balachandran 2011 IEEE Computer Society Annual Symposium on VLSI, 90-95, 2011 | 12 | 2011 |
| Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers B Panda, S Balachandran Computer Architecture Letters, DOI: 10.1109/LCA.2015.2428703, 2015 | 10 | 2015 |
| On metrics for comparing interconnect estimation methods for FPGAs P Kannan, S Balachandran, D Bhatia IEEE transactions on very large scale integration (VLSI) systems 12 (4), 381-385, 2004 | 9 | 2004 |
| Csharp: Coherence and sharing aware cache replacement policies for parallel applications B Panda, S Balachandran 2012 IEEE 24th International Symposium on Computer Architecture and High …, 2012 | 8 | 2012 |
| Set-cover heuristics for two-level logic minimization A Kagliwal, S Balachandran 2012 25th International Conference on VLSI Design, 197-202, 2012 | 8 | 2012 |
| : Cost Based Hardware Optimization for Asymmetric Multicore Processors JKV Sreelatha, S Balachandran, R Nasre IEEE Transactions on Multi-Scale Computing Systems 4 (2), 163-176, 2018 | 7 | 2018 |
| Cupl: A compile-time uncoalesced memory access pattern locator for cuda M Amilkanthwar, S Balachandran Proceedings of the 27th international ACM conference on International …, 2013 | 7 | 2013 |
| Application behavior aware re-reference interval prediction for shared LLC P Lathigara, S Balachandran, V Singh 2015 33rd IEEE International Conference on Computer Design (ICCD), 172-179, 2015 | 6 | 2015 |
| XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests AS Trinadh, S Potluri, S Balachandran, C Babu, V Kamakoti Journal of Low Power Electronics 10 (1), 107-115, 2014 | 6 | 2014 |
| On routing demand and congestion estimation for FPGAs S Balachandran, P Kannan, D Bhatia Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 6 | 2002 |
| Compositional design of stochastic timed automata P Bouyer, T Brihaye, P Carlier, Q Menet International Computer Science Symposium in Russia, 117-130, 2016 | 5 | 2016 |
| CAFFEINE: a utility-driven prefetcher aggressiveness engine for multicores B Panda, S Balachandran ACM Transactions on Architecture and Code Optimization (TACO) 12 (3), 1-25, 2015 | 5 | 2015 |
| An efficient wirelength model for analytical placement BNB Ray, S Balachandran 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 5 | 2013 |
| Hardware prefetchers for emerging parallel applications B Panda, S Balachandran Proceedings of the 21st international conference on Parallel architectures …, 2012 | 5 | 2012 |
Dinesh Bhatiauniversity of texas at dallasVerified email at utdallas.edu
