| Area, Delay and Power Comparison of Adder Topologies SP R.UMA,Vidya Vijayan, M. Mohanapriya International journal of VLSI design & Communication Systems (VLSICS) 3 (01 …, 2012 | 182* | 2012 |
| Low Power Reversible Parallel Binary Adder/Subtractor RKB Rangaraju H G, Venugopal U, Muralidhara K N International journal of VLSI design & Communication Systems (VLSICS) 1 (03 …, 2010 | 98* | 2010 |
| Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design ST Subodh Wairya, Rajendra Kumar Nagaria International journal of VLSI design & Communication Systems (VLSICS) 3 (02 …, 2012 | 67* | 2012 |
| An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System Generator DAK Mrs. S. Allin Christe, Mr.M.Vignesh International journal of VLSI design & Communication Systems (VLSICS) 2 (04 …, 2011 | 67* | 2011 |
| Finite State Machine based Vending Machine Controller with Auto-Billing Features BS Ana Monga International journal of VLSI design & Communication Systems (VLSICS) 3 (02 …, 2012 | 61 | 2012 |
| Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate SP Manoj Kumar, Sandeep K. Arya International journal of VLSI design & Communication Systems (VLSICS) 2 (04 …, 2011 | 58* | 2011 |
| Design of Reversible Sequential Circuit Using Reversible Logic Synthesis MEU Md. Belayet Ali, Md. Mosharof Hossin International journal of VLSI design & Communication Systems (VLSICS) 2 (04 …, 2011 | 54* | 2011 |
| Physical Scaling Limits of FinFET Structure: A Simulation Study AKR Gaurav Saini International journal of VLSI design & Communication Systems (VLSICS) 2 (01 …, 2011 | 54 | 2011 |
| Arithmetic Operations in Multi-Valued Logic k s gurumurthy Vasundara Patel International journal of VLSI design & Communication Systems (VLSICS) 1 (01 …, 2010 | 53* | 2010 |
| Single Electron Transistor: Applications & Problems MK Om Kumar International journal of VLSI design & Communication Systems (VLSICS) 1 (04 …, 2010 | 48 | 2010 |
| New Design Methodologies for High-Speed Mixed-Mode CMOS Full Adder Circuits ST Subodh Wairya, Rajendra Kumar Nagaria International journal of VLSI design & Communication Systems (VLSICS) 2 (02 …, 2011 | 44 | 2011 |
| Leakage Power Reduction and Analysis of CMOS Sequential Circuits SM M. Janaki Rani International journal of VLSI design & Communication Systems (VLSICS) 3 (01 …, 2012 | 42* | 2012 |
| Wishbone Bus Architecture - A Survey and Comparison DK Mohandeep Sharma International journal of VLSI design & Communication Systems (VLSICS) 3 (02 …, 2012 | 41* | 2012 |
| A New Approach to Design Low Power CMOS Flash A/D Converter RC Sudakar S. Chauhan, S. Manabala, S.C. Bose International journal of VLSI design & Communication Systems (VLSICS) 2 (02 …, 2011 | 39* | 2011 |
| Power Comparison of CMOS and Adiabatic Full Adder Circuits VVGSRP Y. Sunil Gavaskar Reddy International journal of VLSI design & Communication Systems (VLSICS) 2 (03 …, 2011 | 38* | 2011 |
| Design of a high frequency low voltage CMOS operational amplifier P Kakoty International journal of VLSI design & Communication Systems (VLSICS) 2 (01 …, 2011 | 38 | 2011 |
| Cell Stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45NM Technology DKP K. Dhanumjaya, M. Sudha, Dr.MN.Giri Prasad International journal of VLSI design & Communication Systems (VLSICS) 3 (02 …, 2012 | 36* | 2012 |
| Design of Reversible Multipliers for Linear Filtering Applications in DSP RTR Rakshith Saligram International Journal Of VLSI Design & Communication Systems ( VLSICS ) 3 …, 2012 | 35* | 2012 |
| Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates MKV H R Bhagyalakshmi International Journal Of VLSI Design & Communication Systems ( VLSICS ) 3 …, 2012 | 35 | 2012 |
| Novel Sleep Transistor Techniques for Low Leakage Power Peripheral Circuits SK Rajani H.P. International Journal Of VLSI Design & Communication Systems ( VLSICS ) 3 …, 2012 | 35 | 2012 |
