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Prasanna Palsodkar, Ph.D
Prasanna Palsodkar, Ph.D
Asst.Prof, Department of Electronics Engineering, YCCE, Nagpur
Verified email at ycce.edu
Title
Cited by
Cited by
Year
Human perception-based color image segmentation using comprehensive learning particle swarm optimization
P Puranik, P Bajaj, A Abraham, P Palsodkar, A Deshmukh
2009 Second International Conference on Emerging Trends in Engineering …, 2009
802009
FPGA implementation of adaptive LMS filter
SS Godbole, PM Palsodkar, VP Raut
Proceedings of SPIT-IEEE Colloquium and International Conference 2, 226-229, 2011
162011
Design and implementation of 64 bit multiplier using vedic algorithm
A Jais, P Palsodkar
2016 International Conference on Communication and Signal Processing (ICCSP …, 2016
142016
Design and implementation of goldschmidts algorithm for floating point division and square root
R Bhoyar, P Palsodkar, S Kakde
2015 International Conference on Communications and Signal Processing (ICCSP …, 2015
112015
Design and verification of dadda algorithm based binary floating point multiplier
V Buddhe, P Palsodkar, P Palsodakar
2014 International Conference on Communication and Signal Processing, 1073-1077, 2014
112014
Improved fused floating point add-subtract and multiply-add unit for FFT implementation
GA Palsodkar Prasanna
2nd International Conference on Devices, Circuits and Systems (ICDCS) 2014, 1-5, 2014
92014
Smart waste management (Swm) systems for offices and educational institutes
P Palsodkar, P Palsodkar, P Dakhole, M Patil
J Adv Res Dyn Control Syst 12 (6), 58-63, 2020
72020
Highly digitalized flash analog to digital (fadc) converter using mux based decoder topology
P Palsodkar, P Dakhole, P Palsodkar, AV Kale
2012 1st International Conference on Emerging Technology Trends in …, 2012
72012
VLSI implementation of a barrel shifter
P Mandal, S Malani, Y Gudepkar, S Singhi, PM Palsodkar
Proceedings of SPIT-IEEE Colloquium and International Conference 2150, 2022
62022
SM-IEEE: Design and implementation of 64 bit multiplier using Vedic algorithm
A Jais, P Palsodkar
international conference on communication and signal processing (ICCSP …, 2016
62016
Research trends in development of floating point computer arithmetic
L Kamble, P Palsodkar, P Palsodkar
2017 International Conference on Communication and Signal Processing (ICCSP …, 2017
42017
Reduced complexity linearity improved threshold quantized comparator based flash ADC
P Palsodkar, P Dakhole, P Palsodkar
Journal of Circuits, Systems and Computers 26 (03), 1750046, 2017
42017
Floating Point-based Universal Fused Add–Subtract Unit
IA Patil, P Palsodkar, A Gurjar
Proceedings of the Second International Conference on Soft Computing for …, 2014
42014
Improved power supply rejection (PSR) digital comparator based Flash analog to digital converter (FADC)
P Palsodkar, PK Dakhole, P Palsodkar
2014 International Conference on Electronics and Communication Systems …, 2014
32014
An approach for four way set associative multilevel CMOS cache memory
P Palsodkar, A Deshmukh, P Bajaj, AG Keskar
International Conference on Knowledge-Based and Intelligent Information and …, 2007
32007
Multiple Error Self Checking-Repairing Fault Tolerant Adder-Multiplier
P Palsodkar, P Palsodkar, R Giri
2018 IEEE Region 10 Humanitarian Technology Conference (R10-HTC), 1-4, 2018
22018
BSD adder for floating point arithmetic: A review
R Watpade, P Palsodkar
2017 International Conference on Communication and Signal Processing (ICCSP …, 2017
22017
Implementation of three operand floating point adder
O Narule, P Palsodkar
2016 International Conference on Communication and Signal Processing (ICCSP …, 2016
22016
Implementation of fused floating point three term adder unit
M Popalghat, P Palsodkar
2016 International Conference on Communication and Signal Processing (ICCSP …, 2016
22016
Prachi Palsodkar Aniket Gokhale An Approach to Extract Salient Regions by Segmenting Color Images using Soft Computing Techniques
P Palsodkar
International Conference on VLSI, Communication & Instrumentation (ICVCI), 2011
22011
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