| Energy efficient CMOS Full-Adder Designed with TSMC 0.18 μm Technology V Vijay, J Prathiba, SN Reddy, VR Rao International Conference on Technology and Management (ICTM-2011), Hyderabad …, 2011 | 55 | 2011 |
| A review of the 0.09 µm standard full adders V Vijay, J Prathiba, S Niranjan Reddy International Journal of VLSI Design & Communication Systems 3 (3), 119-137, 2012 | 32 | 2012 |
| Effect of plant populations on the performance of maize hybrids at different fertility levels in a semi-arid environment. BB Reddy, RN Reddy, VM Reddy, MR Reddy, A Kumar, KB Swamy | 28 | 1987 |
| Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology N Kandasamy, F Ahmad, S Reddy, N Telagam, S Utlapalli Microprocessors and Microsystems 59, 15-28, 2018 | 22 | 2018 |
| Performance evaluation of the CMOS Full adders in TDK 90 nm Technology V Vijay, J Prathiba, SN Reddy, C Srivalli, BS Reddy International Journal of Systems, Algorithms & Applications 2 (1), 7, 2012 | 20 | 2012 |
| Performance analysis of low power and high speed 16-Bit CRC Generator using GDI technique K Nehru, MR Babu, J Sravana, SR Reddy Advanced Computing and Communication Systems (ICACCS), 2016 3rd …, 2016 | 5 | 2016 |
| A. Professor, High speed full adder design with analog switch level restoration technique S Koniki, U Somanaidu, S Reddy Int. J. Creative Res. Thoughts 6 (1), 370, 2018 | 2 | 2018 |
| VISUAL DISTORTION EFFECTS WITH IMAGE PROCESSING IN MATLAB BY USING NOT GATE LOGIC S Reddy, DS Naga jyothi, S Swathi Journal of Advanced Research in Dynamical and Control Systems 9 (18), 269-279, 2017 | | 2017 |
| Evaluation of Power from Solar Panels Utilization and Power Theft Identification System S Reddy, NSR MD Mastan Ali www.ijareeie.com 5 (Issue 2), 955-959, 2016 | | 2016 |
| Performance Analysis of Array Multiplier Using SPL and Control Input Technique Based Adder Cells for Neural Networks K Nehru, BM Ramesh, SR Kilaru Seetaiah International Journal of Control Theory and Applications 8 (5), 2189-2194, 2015 | | 2015 |
| Performance Analysis of Array Multiplier Using SPL. and Control Input Technique K Nehru, MR Babu, S Kilaru, S Reddy | | |
Nehru KandasamyMadanapalle Institute of Technology and ScienceVerified email at mits.ac.in
