Nitin Chandrachoodan
Nitin Chandrachoodan
Verified email at ee.iitm.ac.in - Homepage
Title
Cited by
Cited by
Year
FPGA-based high-performance and scalable block LU decomposition architecture
MK Jaiswal, N Chandrachoodan
IEEE Transactions on Computers 61 (1), 60-72, 2011
492011
GPU implementation of a programmable turbo decoder for software defined radio applications
DRN Yoge, N Chandrachoodan
2012 25th International Conference on VLSI Design, 149-154, 2012
272012
Adaptive negative cycle detection in dynamic graphs
N Chandrachoodan, SS Bhattacharyya, KJR Liu
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001
182001
Implementation of a 30 ps resolution time to digital converter in FPGA
R Narasimman, A Prabhakar, N Chandrachoodan
2015 International Conference on Electronic Design, Computer Networks …, 2015
122015
Efficient implementation of IEEE double precision floating-point multiplier on FPGA
MK Jaiswal, N Chandrachoodan
2008 IEEE Region 10 and the Third international Conference on Industrial and …, 2008
102008
Algorithm and VLSI architecture for high performance adaptive video scaling
A Raghupathy, N Chandrachoodan, KJR Liu
IEEE transactions on multimedia 5 (4), 489-502, 2003
102003
DFT assisted techniques for peak launch-to-capture power reduction during launch-on-shift at-speed testing
S Potluri, AS Trinadh, V Kamakoti, N Chandrachoodan
ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (1 …, 2015
92015
A GPU implementation of belief propagation decoder for polar codes
N Chandrachoodan
2012 Conference Record of the Forty Sixth Asilomar Conference on Signals …, 2012
92012
Probabilistic error modeling for two-part segmented approximate adders
D Celia, V Vasudevan, N Chandrachoodan
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
82018
Optimizing power-accuracy trade-off in approximate adders
D Celia, V Vasudevan, N Chandrachoodan
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
72018
Layout-aware and programmable memory BIST synthesis for nanoscale system-on-chip designs
A Kokrady, CP Ravikumar, N Chandrachoodan
2008 17th Asian Test Symposium, 351-356, 2008
72008
An efficient timing model for hardware implementation of multirate dataflow graphs
N Chandrachoodan, SS Bhattacharyaa, KJR Liu
2001 IEEE International Conference on Acoustics, Speech, and Signal …, 2001
72001
The hierarchical timing pair model for multirate DSP applications
N Chandrachoodan, SS Bhattacharyya, KJR Liu
IEEE Transactions on Signal Processing 52 (5), 1209-1217, 2004
62004
FFT/IFFT implementation using Vivado™ HLS
A Salaskar, N Chandrachoodan
2016 20th International Symposium on VLSI Design and Test (VDAT), 1-2, 2016
52016
An inertial sensor-based system to develop motor capacity in children with cerebral palsy
S Qiao, A Prabhakar, N Chandrachoodan, N Jacob, H Vathsangam
2013 35th Annual International Conference of the IEEE Engineering in …, 2013
52013
Speeding up Computation of the max/min of a set of Gaussians for Statistical Timing Analysis and Optimization
V Kuruvilla, D Sinha, J Piaget, C Visweswariah, N Chandrachoodan
Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013
52013
Efficient implementation of floating-point reciprocator on FPGA
MK Jaiswal, N Chandrachoodan
2009 22nd International Conference on VLSI Design, 267-271, 2009
52009
Negative cycle detection in dynamic graphs
N Chandrachoodan, SS Bhattacharyya, KJ Liu
51999
Scenario-aware dynamic power reduction using bias addition
S Rangachari, J Balakrishnan, N Chandrachoodan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 450-461, 2016
32016
Non-uniform dft implementation for channel simulations in gpu
K Natarajan, N Chandrachoodan
2015 Twenty First National Conference on Communications (NCC), 1-6, 2015
32015
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