Sourav Das

201920202021202220231 1 9 3 6

Chester RebeiroIndian Institute of Technology MadrasVerified email at cs.columbia.edu
Kamakoti VeezhinathanProfessor, Department of Computer Science, IIT MadrasVerified email at cse.iitm.ac.in
Arjun MenonInCore Semiconductors Pvt. Ltd.Verified email at incoresemi.com
Sayandeep SanyalSenior Formal Verification Engineer, QualcommVerified email at ieee.org
Aritra HazraAssistant Professor, Department of Computer Science and Engineering, IIT KharagpurVerified email at cse.iitkgp.ac.in
Pallab DasguptaIndian Institute of Technology KharagpurVerified email at cse.iitkgp.ac.in

Sourav Das

Verified email at iitkgp.ac.in


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SHAKTI-MS: a RISC-V processor for memory safety in C S Das, RH Unnithan, A Menon, C Rebeiro, K Veezhinathan Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on …, 2019	19	2019
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits S Sanyal, P Dasgupta, A Hazra, S Das, S Morrison, S Surendran, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022	1	2022
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications S Das, S Sanyal, A Hazra, P Dasgupta ACM Transactions on Design Automation of Electronic Systems 28 (1), 1-32, 2022		2022

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