Shobha Vasudevan
Shobha Vasudevan
Professor of Computer Engineering, University of Illinois at Urbana-Champaign
Verified email at illinois.edu - Homepage
Title
Cited by
Cited by
Year
Goldmine: Automatic assertion generation using data mining and static analysis
S Vasudevan, D Sheridan, S Patel, D Tcheng, B Tuohy, D Johnson
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1312010
Efficient validation input generation in RTL by hybridized source code analysis
L Liu, S Vasudevan
2011 Design, Automation & Test in Europe, 1-6, 2011
702011
Mining hardware assertions with guidance from static analysis
S Hertz, D Sheridan, S Vasudevan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
612013
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor
S Gurumurthy, S Vasudevan, JA Abraham
2006 IEEE International Test Conference, 1-9, 2006
592006
Integration of data mining and static analysis for hardware design verification
S Vasudevan, D Sheridan, L Liu
US Patent 9,021,409, 2015
572015
Automated mapping of pre-computed module-level test sequences to processor instructions
S Guramurthy, S Vasudevan, JA Abraham
IEEE International Conference on Test, 2005., 10 pp.-303, 2005
542005
Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems
S Vasudevan, V Viswanath, RW Sumners, JA Abraham
IEEE Transactions on Computers 56 (10), 1401-1414, 2007
402007
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
S Vasudevan, JA Abraham, V Viswanath, J Tu
Fourth ACM and IEEE International Conference on Formal Methods and Models …, 2006
372006
Can't see the forest for the trees: State restoration's limitations in post-silicon trace signal selection
S Ma, D Pal, R Jiang, S Ray, S Vasudevan
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2015
352015
STAR: Generating input vectors for design validation by static analysis of RTL
L Liu, S Vasudevan
2009 IEEE International High Level Design Validation and Test Workshop, 32-37, 2009
282009
Application level investigation of system-level ESD-induced soft failures
S Vora, R Jiang, S Vasudevan, E Rosenbaum
2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2016
272016
Automatic generation of assertions from system level design using data mining
L Liu, D Sheridan, V Athavale, S Vasudevan
Ninth ACM/IEEE International Conference on Formal Methods and Models for …, 2011
252011
Improved verification of hardware designs through antecedent conditioned slicing
S Vasudevan, EA Emerson, JA Abraham
International Journal on Software Tools for Technology Transfer 9 (1), 89-101, 2007
242007
Efficient model checking of hardware using conditioned slicing
S Vasudevan, EA Emerson, JA Abraham
Electronic Notes in Theoretical Computer Science 128 (6), 279-294, 2005
242005
Word level feature discovery to enhance quality of assertion mining
L Liu, CH Lin, S Vasudevan
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 210-217, 2012
232012
Towards coverage closure: Using goldmine assertions for generating design validation stimulus
L Liu, D Sheridan, W Tuohy, S Vasudevan
2011 Design, Automation & Test in Europe, 1-6, 2011
232011
A technique for test coverage closure using goldmine
L Liu, D Sheridan, W Tuohy, S Vasudevan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
222012
A coverage guided mining approach for automatic generation of succinct assertions
D Sheridan, L Liu, H Kim, S Vasudevan
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
192014
Scaling input stimulus generation through hybrid static and dynamic analysis of RTL
L Liu, S Vasudevan
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1 …, 2014
182014
Merit-based characterization of assertions in hardware design verification
S Vasudevan, S Hertz
US Patent 9,075,935, 2015
172015
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