| An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With W/Channel in 65-nm CMOS AT Do, SMA Zeinolabedin, D Jeon, D Sylvester, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 126-137, 2018 | 44 | 2018 |
| A 16-Channel Fully Configurable Neural SoC With 1.52 W/Ch Signal Acquisition, 2.79 W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural … SMA Zeinolabedin, FM Schüffny, R George, F Kelber, H Bauer, S Scholze, ... IEEE Transactions on Biomedical Circuits and Systems 16 (1), 94-107, 2022 | 36 | 2022 |
| A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS SMA Zeinolabedin, AT Do, D Jeon, D Sylvester, TH Kim Symposium on VLSI Circuits, 2016 | 29 | 2016 |
| Real-time hardware implementation of arm coresight trace decoder SMA Zeinolabedin, J Partzsch, C Mayr IEEE Design & Test 38 (1), 69-77, 2020 | 13 | 2020 |
| Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits SMA Zeinolabedin, AT Do, KS Yeo, TTH Kim 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 794-797, 2015 | 12 | 2015 |
| Energy-efficient data-aware SRAM design utilizing column-based data encoding AT Do, SMA Zeinolabedin, TTH Kim IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2154-2158, 2019 | 11 | 2019 |
| An area-and energy-efficient FIFO design using error-reduced data compression and near-threshold operation for image/video applications SMA Zeinolabedin, J Zhou, X Liu, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014 | 10 | 2014 |
| A 64-channel back-gate adapted ultra-low-voltage spike-aware neural recording front-end with on-chip lossless/near-lossless compression engine and 3.3 v stimulator in 22nm fdsoi FM Schüffny, SMA Zeinolabedin, R George, L Guo, A Weiße, J Uhlig, ... 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022 | 8 | 2022 |
| Low computational complexity hardware implementation of Laplacian Pyramid SMA Zeinolabedin, N Karimi, S Samavi 2010 18th Iranian Conference on Electrical Engineering, 465-470, 2010 | 8 | 2010 |
| An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology F Schüffny, S Höppner, S Hänzsche, RM George, SMA Zeinolabedin, ... IEEE Transactions on Circuits and Systems II: Express Briefs, 2021 | 7 | 2021 |
| Analyzing ARM CoreSight ETMV4.X Data Trace Stream with a Real-Time Hardware Accelerator SMA Zeinolabedin, J Partzsch, C Mayr Design, Automation and Test in Europe Conference, 2021 | 5 | 2021 |
| Contourlet based image compression using controlled modification of coefficients N Karimi, S Samavi, S Shirani, H Talebi, SMA Zaynolabedin 2009 Canadian Conference on Electrical and Computer Engineering, 991-994, 2009 | 5 | 2009 |
| Various distance metrics evaluation on neural spike classification S Guo, L Guo, SMA Zeinolabedin, C Mayr 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), 554-558, 2022 | 4 | 2022 |
| A 0.3 PJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications AT Do, SMA Zeinolabedin, TT Kim 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 173-176, 2016 | 4 | 2016 |
| Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression Q Ma, L Guo, SMA Zeinolabedin, C Mayr IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021 | 3 | 2021 |
| An area-and power-efficient FIFO with error-reduced data compression for image/video processing SMA Zeinolabedin, J Zhou, X Liu, TT Kim 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2277-2280, 2014 | 3 | 2014 |
| A new quantization algorithm for fir filters coefficients SMA Zeinolabedin, N Karimi 20th Iranian Conference on Electrical Engineering (ICEE2012), 1120-1124, 2012 | 3 | 2012 |
| 68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI L Guo, A Weiße, SMA Zeinolabedin, FM Schüffny, M Stolba, Q Ma, ... Frontiers in Neuroscience 18, 1432750, 2024 | 2 | 2024 |
| A 3.3 V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI FM Schüffny, S Hänzsche, S Henker, SMA Zeinolabedin, S Scholze, ... 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5, 2023 | 2 | 2023 |
| A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI L Guo, SMA Zeinolabedin, FM Schüffny, A Weiße, S Scholze, R George, ... 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5, 2023 | 2 | 2023 |
Tony Tae-Hyoung KIMAssociate Professor, Nanyang Technological UniversityVerified email at ntu.edu.sg
