| Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS R Vaddi, S Dasgupta, RP Agarwal IEEE Transactions on Electron Devices 57 (3), 654-664, 2010 | 130 | 2010 |
| Tunnel FET RF rectifier design for energy harvesting applications H Liu, X Li, R Vaddi, K Ma, S Datta, V Narayanan IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014 | 91 | 2014 |
| Device and circuit design challenges in the digital subthreshold region for ultralow-power applications R Vaddi, S Dasgupta, RP Agarwal VLSI Design 2009, 2009 | 53 | 2009 |
| The shuttle nanoelectromechanical nonvolatile memory V Pott, GL Chua, R Vaddi, JML Tsai, TT Kim IEEE transactions on electron devices 59 (4), 1137-1143, 2012 | 50 | 2012 |
| Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier H Liu, R Vaddi, S Datta, V Narayanan International Symposium on Low Power Electronics and Design (ISLPED), 157-162, 2013 | 40 | 2013 |
| Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options R Vaddi, RP Agarwal, S Dasgupta Microelectronics journal 42 (5), 798-807, 2011 | 34 | 2011 |
| Compact modeling of a generic double-gate MOSFET with gate–S/D underlap for subthreshold operation R Vaddi, RP Agarwal, S Dasgupta IEEE transactions on electron devices 59 (10), 2846-2849, 2012 | 28 | 2012 |
| Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic R Vaddi, S Dasgupta, RP Agarwal Microelectronics journal 41 (4), 195-211, 2010 | 26 | 2010 |
| Design and analysis of double-gate mosfets for ultra-low power radio frequency identification (rfid): Device and circuit co-design R Vaddi, RP Agarwal, S Dasgupta, TT Kim Journal of Low Power Electronics and Applications 1 (2), 277-302, 2011 | 24 | 2011 |
| Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction A Japa, H Vallabhaneni, R Vaddi IET Circuits, Devices & Systems 10 (6), 522-527, 2016 | 18 | 2016 |
| Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm H Vallabhaneni, A Japa, S Shaik, KSR Krishna, R Vaddi 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-5, 2014 | 17 | 2014 |
| Low power nanoelectronics H Liu, R Vaddi, V Narayanan, S Datta, MS Kim, X Li, A Schmid, ... US Patent 9,800,094, 2017 | 16 | 2017 |
| Design and scalability of a memory array utilizing anchor-free nanoelectromechanical nonvolatile memory device R Vaddi, V Pott, GL Chua, JTM Lin, TT Kim IEEE electron device letters 33 (9), 1315-1317, 2012 | 12 | 2012 |
| Circuit and architectural co-design for reliable adder cells with steep slope tunnel transistors for energy efficient computing S Shaik, KSR Krishna, R Vaddi 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 11 | 2016 |
| Tunnel FET based low voltage static vs dynamic logic families for energy efficiency K Subramanyam, S Shaik, R Vaddi 18th International Symposium on VLSI Design and Test, 1-2, 2014 | 11 | 2014 |
| Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs G Kaushal, K Subramanyam, SN Rao, G Vidya, R Ramya, S Shaik, ... 2014 International SoC Design Conference (ISOCC), 32-33, 2014 | 9 | 2014 |
| Enhanced bias-flip rectifier with ultra-low power control for piezo electric energy harvester in the microwatt application scenario R Vaddi, S Dasgupta 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics …, 2012 | 8 | 2012 |
| Tunneling field effect transistors for enhancing energy efficiency and hardware security of IoT platforms: challenges and opportunities J Aditya, T Nagateja, SK Vishvakarma, P Yellappa, JR Choi, R Vaddi 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 7 | 2018 |
| Power rectifier using tunneling field effect transistor H Liu, R Vaddi, V Narayanan, S Datta US Patent 9,391,068, 2016 | 7 | 2016 |
| Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks A Japa, MK Majumder, SK Sahoo, R Vaddi IET Circuits, Devices & Systems 13 (5), 689-695, 2019 | 6 | 2019 |
Aditya JapaPh.D. scholar, ECE, IIIT NAYA RAIPURVerified email at iiitnr.edu.in
