| CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs B Li, L Zhao, R Iyer, LS Peh, M Leddige, M Espig, SE Lee, D Newell Journal of Parallel and Distributed Computing 71 (5), 700-713, 2011 | 138 | 2011 |
| A variable frequency link for a power-aware network-on-chip (NoC) SE Lee, N Bagherzadeh Integration 42 (4), 479-485, 2009 | 102 | 2009 |
| DMesh: a diagonally-linked mesh network-on-chip architecture WH Hu, SE Lee, N Bagherzadeh Network on Chip Architectures, 14, 2008 | 64 | 2008 |
| On design and analysis of a feasible network-on-chip (noc) architecture JH Bahn, SE Lee, N Bagherzadeh Fourth International Conference on Information Technology (ITNG'07), 1033-1038, 2007 | 56 | 2007 |
| Pipelined cpu design with fpga in teaching computer architecture JH Lee, SE Lee, HC Yu, T Suh IEEE Transactions on Education 55 (3), 341-348, 2011 | 55 | 2011 |
| A high level power model for Network-on-Chip (NoC) router SE Lee, N Bagherzadeh Computers & Electrical Engineering 35 (6), 837-845, 2009 | 51 | 2009 |
| Accelerating mobile augmented reality on a handheld platform SE Lee, Y Zhang, Z Fang, S Srinivasan, R Iyer, D Newell 2009 IEEE International Conference on Computer Design, 419-426, 2009 | 50 | 2009 |
| Increasing the throughput of an adaptive router in network-on-chip (NoC) SE Lee, N Bagherzadeh Proceedings of the 4th international conference on Hardware/software …, 2006 | 50 | 2006 |
| Implementation of Internet-based personal robot with Internet control architecture KH Han, S Kim, YJ Kim, SE Lee, JH Kim Proceedings 2001 ICRA. IEEE International Conference on Robotics and …, 2001 | 49 | 2001 |
| Buffer-integrated-cache: a cost-effective sram architecture for handheld and embedded platforms CF Fajardo, Z Fang, R Iyer, GF Garcia, SE Lee, L Zhao Proceedings of the 48th Design Automation Conference, 966-971, 2011 | 45 | 2011 |
| Area and power-efficient innovative congestion-aware Network-on-Chip architecture C Wang, WH Hu, SE Lee, N Bagherzadeh Journal of Systems Architecture 57 (1), 24-38, 2011 | 43 | 2011 |
| Cogniserve: Heterogeneous server architecture for large-scale recognition R Iyer, S Srinivasan, O Tickoo, Z Fang, R Illikkal, S Zhang, V Chadha, ... IEEE Micro, 20-31, 2011 | 42 | 2011 |
| Parallel and pipeline processing for block cipher algorithms on a network-on-chip YS Yang, JH Bahn, SE Lee, N Bagherzadeh 2009 Sixth International Conference on Information Technology: New …, 2009 | 39 | 2009 |
| Accelerating Histograms of Oriented Gradients descriptor extraction for pedestrian recognition SE Lee, K Min, T Suh Computers & Electrical Engineering 39 (4), 1043-1048, 2013 | 38 | 2013 |
| A generic network interface architecture for an NoC based multiprocessor SoC SE Lee, JH Bahn, YS Yang, N Bagherzadeh Int. Symp. on Architecture of Computing System, 247-260, 2008 | 34* | 2008 |
| Low-power, resilient interconnection with Orthogonal Latin Squares SE Lee, YS Yang, GS Choi, W Wu, R Iyer IEEE Design & Test of Computers 28 (2), 30-39, 2011 | 33 | 2011 |
| Secure communication system for wearable devices wireless intra body communication SD Kim, SM Lee, SE Lee 2015 IEEE international conference on consumer electronics (ICCE), 381-382, 2015 | 30 | 2015 |
| A generic network interface architecture for a networked processor array (NePA) SE Lee, JH Bahn, YS Yang, N Bagherzadeh International Conference on Architecture of Computing Systems, 247-260, 2008 | 30 | 2008 |
| On design and application mapping of a Network-on-Chip (NoC) architecture JH Bahn, SE Lee, YS Yang, J Yang, N Bagherzadeh Parallel Processing Letters 18 (02), 239-255, 2008 | 27 | 2008 |
| Design of a feasible on-chip interconnection network for a chip multiprocessor (cmp) SE Lee, JH Bahn, N Bagherzadeh 19th International Symposium on Computer Architecture and High Performance …, 2007 | 20 | 2007 |
Nader BagherzadehProfessor of EECS, UC IrvineVerified email at uci.edu
