| Neural trojans Y Liu, Y Xie, A Srivastava 2017 IEEE International Conference on Computer Design (ICCD), 45-48, 2017 | 356 | 2017 |
| Reverse Engineering-based Hardware Trojan Detection C Bao, D Forte, Y Liu, A Srivastava The Hardware Trojan War, 269, 2018 | 181 | 2018 |
| Keynote: A disquisition on logic locking A Chakraborty, NG Jayasankaran, Y Liu, J Rajendran, O Sinanoglu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 107 | 2019 |
| A Survey on Neural Trojans Y Liu, A Mondal, A Chakraborty, M Zuzak, N Jacobsen, D Xing, ... 2020 21st International Symposium on Quality Electronic Design (ISQED), 33-39, 2020 | 85 | 2020 |
| Strong Anti-SAT: Secure and Effective Logic Locking Y Liu, M Zuzak, Y Xie, A Chakraborty, A Srivastava 2020 21st International Symposium on Quality Electronic Design (ISQED), 199-205, 2020 | 51 | 2020 |
| TimingSAT: Timing profile embedded SAT attack A Chakraborty, Y Liu, A Srivastava 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018 | 41 | 2018 |
| A combined optimization-theoretic and side-channel approach for attacking strong physical unclonable functions Y Liu, Y Xie, C Bao, A Srivastava IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 73-81, 2017 | 32 | 2017 |
| Ganred: Gan-based reverse engineering of dnns via cache side-channel Y Liu, A Srivastava Proceedings of the 2020 ACM SIGSAC Conference on Cloud Computing Security …, 2020 | 28 | 2020 |
| Mitigating reverse engineering attacks on deep neural networks Y Liu, D Dachman-Soled, A Srivastava 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 657-662, 2019 | 27 | 2019 |
| Robust and attack resilient logic locking with a high application-level impact Y Liu, M Zuzak, Y Xie, A Chakraborty, A Srivastava ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-22, 2021 | 19 | 2021 |
| 2.5 D/3D integration technologies for circuit obfuscation Y Xie, C Bao, Y Liu, A Srivastava 2016 17th International Workshop on Microprocessor and SOC Test and …, 2016 | 19 | 2016 |
| Trace logic locking: Improving the parametric space of logic locking M Zuzak, Y Liu, A Srivastava IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 16 | 2020 |
| A Resource Binding Approach to Logic Obfuscation M Zuzak, Y Liu, A Srivastava 2021 58th ACM/IEEE Design Automation Conference (DAC), 235-240, 2021 | 9 | 2021 |
| Introducing TFUE: The trusted foundry and untrusted employee model in IC supply chain security Y Liu, C Bao, Y Xie, A Srivastava 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 8 | 2017 |
| Evaluating the security of delay-locked circuits A Chakraborty, Y Liu, A Srivastava IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 7 | 2020 |
| An optimization-theoretic approach for attacking physical unclonable functions Y Liu, Y Xie, C Bao, A Srivastava 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016 | 7 | 2016 |
| A combined logical and physical attack on logic obfuscation M Zuzak, Y Liu, I McDaniel, A Srivastava Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 4 | 2022 |
| A Survey on Side-Channel-based Reverse Engineering Attacks on Deep Neural Networks Y Liu, M Zuzak, D Xing, I McDaniel, P Mittu, O Ozbay, A Akib, A Srivastava 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 3 | 2022 |
| Dynamarks: Defending against deep learning model extraction using dynamic watermarking A Chakraborty, D Xing, Y Liu, A Srivastava arXiv preprint arXiv:2207.13321, 2022 | 2 | 2022 |
| Independent Verification and Validation of Security-Aware EDA Tools and IP B Tan, S Garg, R Karri, Y Liu, M Zuzak, A Chakraborty, A Srivastava, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 1299-1302, 2021 | 1 | 2021 |
Ankur SrivastavaUniversity of MarylandVerified email at umd.edu
