| Advanced modes in AES: Are they safe from power analysis based side channel attacks? D Jayasinghe, R Ragel, JA Ambrose, A Ignjatovic, S Parameswaran 2014 IEEE 32nd International Conference on Computer Design (ICCD), 173-180, 2014 | 47 | 2014 |
| Remote cache timing attack on advanced encryption standard and countermeasures D Jayasinghe, J Fernando, R Herath, R Ragel 2010 Fifth International Conference on Information and Automation for …, 2010 | 28 | 2010 |
| RFTC: Runtime frequency tuning countermeasure using FPGA dynamic reconfiguration to mitigate power analysis attacks D Jayasinghe, A Ignjatovic, S Parameswaran Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 24 | 2019 |
| Constant time encryption as a countermeasure against remote cache timing attacks D Jayasinghe, R Ragel, D Elkaduwe 2012 IEEE 6th International Conference on Information and Automation for …, 2012 | 21 | 2012 |
| Side channel attacks in embedded systems: A tale of hostilities and deterrence JA Ambrose, RG Ragel, D Jayasinghe, T Li, S Parameswaran Sixteenth International Symposium on Quality Electronic Design, 452-459, 2015 | 19 | 2015 |
| Quadseal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks D Jayasinghe, A Ignjatovic, JA Ambrose, R Ragel, S Parameswaran 2015 International Conference on Compilers, Architecture and Synthesis for …, 2015 | 18 | 2015 |
| Countermeasures against Bernstein's remote cache timing attack J Alawatugoda, D Jayasinghe, R Ragel 2011 6th International Conference on Industrial and Information Systems, 43-48, 2011 | 18 | 2011 |
| Accelerating correlation power analysis using graphics processing units (gpus) H Gamaarachchi, R Ragel, D Jayasinghe 7th International Conference on Information and Automation for …, 2014 | 11 | 2014 |
| VITI: A tiny self-calibrating sensor for power-variation measurement in FPGAs B Udugama, D Jayasinghe, H Saadat, A Ignjatovic, S Parameswaran IACR Transactions on Cryptographic Hardware and Embedded Systems, 657-678, 2022 | 9 | 2022 |
| SCRIP: Secure random clock execution on soft processor systems to mitigate power-based side channel attacks D Jayasinghe, A Ignjatovic, S Parameswaran 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2019 | 8 | 2019 |
| NORA: Algorithmic balancing without pre-charge to thwart power analysis attacks D Jayasinghe, A Ignjatovic, S Parameswaran 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 8 | 2017 |
| Uclod: Small clock delays to mitigate remote power analysis attacks D Jayasinghe, A Ignjatovic, S Parameswaran IEEE Access 9, 108411-108425, 2021 | 7 | 2021 |
| Randomised multi‐modulo residue number system architecture for double‐and‐add to prevent power analysis side channel attacks JA Ambrose, H Pettenghi, D Jayasinghe, L Sousa IET Circuits, Devices & Systems 7 (5), 283-293, 2013 | 7 | 2013 |
| Scalable performance monitoring of application specific multiprocessor Systems-on-Chip JA Ambrose, V Cassisi, D Murphy, T Li, D Jayasinghe, S Parameswaran 2013 IEEE 8th International Conference on Industrial and Information Systems …, 2013 | 6 | 2013 |
| A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks A Arora, S Parameswaran, R Ragel, D Jayasinghe 2011IEEE 10th International Conference on Trust, Security and Privacy in …, 2011 | 6 | 2011 |
| Quadseal: Quadruple balancing to mitigate power analysis attacks with variability effects and electromagnetic fault injection attacks D Jayasinghe, A Ignjatovic, R Ragel, JA Ambrose, S Parameswaran ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (5 …, 2021 | 5 | 2021 |
| LFTSM: Lightweight and fully testable SEU mitigation system for Xilinx processor-based SoCs F Abid, D Jayasinghe, S Somsavaddy, S Parameswaran 2020 30th International Conference on Field-Programmable Logic and …, 2020 | 5 | 2020 |
| FPGA Based Countermeasures Against Side channel Attacks on Block Ciphers D Jayasinghe, B Udugama, S Parameswaran Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 2 | 2023 |
| A power to pulse width modulation sensor for remote power analysis attacks B Udugama, D Jayasinghe, H Saadat, A Ignjatovic, S Parameswaran IACR Transactions on Cryptographic Hardware and Embedded Systems, 589-613, 2022 | 2 | 2022 |
| Template attacks with partial profiles and Dirichlet priors: Application to timing attacks E De Cherisey, S Guilley, O Rioul, D Jayasinghe Proceedings of the Hardware and Architectural Support for Security and …, 2016 | 1 | 2016 |
Aleksandar IgnjatovicUniversity of New South WalesVerified email at cse.unsw.edu.au
