| Implementation of area and energy efficient Full adder cell N Tiwari, R Sharma, R Parihar International Conference on Recent Advances and Innovations in Engineering …, 2014 | 18 | 2014 |
| An implementation of 1-bit low power full adder based on multiplexer and pass transistor logic R Parihar, N Tiwari, A Mandloi, B Kumar International Conference on Information Communication and Embedded Systems …, 2014 | 14 | 2014 |
| Detection and Classification of Tumor Type in Brain MRI images using SVM & Deep Learning VS Sujata,Rajesh Parihar Scopus 16 (X), 9, 2020 | | 2020 |
| IMPLEMENTATION OF AREA EFFICIENT CARRY LOOK AHEAD ADDER IN GDI TECHNOLOGY RP Tanisha Tomar JETIR 5 (7), 10, 2018 | | 2018 |
| IMPLEMENTATION OF LOW POWER HALF ADDER IN GDI TECHNOLOGY RP Tanisha Tomar JETIR 5 (6), 6, 2018 | | 2018 |
| Design of a Low Power, High Performance Redundant Binary Full Adder Using a Novel Approach in 130nm, 120nm CMOS Technology. R Parihar, B Kumar VCAN, 2015 | | 2015 |
| IMPROVED HIGH SPEED IMPLEMENTATION OF FAST ALU USING REDUNDANT BINARY NUMBERS FOR SIGNED AND UNSIGNED NUMBERS R Parihar, B Kumar INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER SCIENCE AND MANAGEMENT …, 2014 | | 2014 |
| Implementation of area and energy efficient Full adder cell R Sharma, N Tiwari, R Parihar | | |
Dr. Binod KumarJayawant Shikshan Prasarak Mandal Rajarshi Shahu College of Engineering , Pune, IndiaVerified email at ieee.org
