Dr. Gopi Krishna Saramekala
Dr. Gopi Krishna Saramekala
Verified email at nitc.ac.in
Title
Cited by
Cited by
Year
An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs
S Dubey, A Santra, G Saramekala, M Kumar, PK Tiwari
IEEE Transactions on Nanotechnology 12 (5), 766-774, 2013
412013
An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET
GK Saramekala, A Santra, S Dubey, S Jit, PK Tiwari
Superlattices and Microstructures 60, 580-595, 2013
212013
Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs
GK Saramekala, A Santra, M Kumar, S Dubey, S Jit, PK Tiwari
Journal of Computational Electronics 13 (2), 467-476, 2014
122014
Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs
GK Saramekala, S Dubey, PK Tiwari
Superlattices and Microstructures 76, 77-89, 2014
72014
Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates
PK Tiwari, GK Saramekala, S Dubey, AK Mukhopadhyay
Journal of Semiconductors 35 (10), 104002, 2014
62014
A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric
GK Saramekala, S Dubey, PK Tiwari
Chinese Physics B 24 (10), 108505, 2015
52015
Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs
PK Tiwari, M Kumar, RS Naik, GK Saramekala
Journal of Semiconductors 37 (6), 064003, 2016
42016
Analog and RF performance evaluation of negative capacitance SOI junctionless transistor
S Moparthi, KP Adarsh, PK Tiwari, GK Saramekala
AEU-International Journal of Electronics and Communications 122, 153243, 2020
32020
An analytical threshold voltage model of fully depleted (FD) recessed-source/drain (re-S/D) SOI MOSFETs with Back-gate control
GK Saramekala, PK Tiwari
Journal of Electronic Materials 45 (10), 5367-5374, 2016
32016
Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO 2| La 2 O 3| HfO 2 (HLH) Sandwich Gate Dielectrics
L Ramesh, S Moparthi, PK Tiwari, VR Samoju, GK Saramekala
Semiconductors 54 (10), 1290-1295, 2020
22020
A Two-Dimensional Subthreshold Current Model of Recessed-Source/Drain (Re-S/D) SOI MOSFETs with High-k Dielectric
GK Saramekala, PK Tiwari
2014 8th Asia Modelling Symposium, 258-263, 2014
22014
ATLAS™ based simulation study of the electrical characteristics of dual-metal-gate (DMG) fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs
GK Saramekala, S Jit, PK Tiwari
2014 International Conference on Advances in Electrical Engineering (ICAEE), 1-4, 2014
12014
Genetic algorithm-based threshold voltage prediction of SOI JLT using multi-variable nonlinear regression
S Moparthi, PK Tiwari, GK Saramekala
2021 International Symposium on Devices, Circuits and Systems (ISDCS), 1-4, 2021
2021
Investigation of Subthreshold Characteristics of Negative Capacitance Single-Active Layer Double-Gate (NC-SALDG) Thin-Film Transistor (TFT)
S Moparthi, R Lavudi, SR Suddapalli, GK Saramekala
Silicon, 1-6, 2021
2021
Machine Learning Based Device Simulation Using Multi-variable Non-linear Regression to Assess the Impact of Device Parameter Variability on Threshold Voltage of Double Gate-Allá…
S Moparthi, C Yadav, GK Saramekala, PK Tiwari
2020 IEEE 2nd International Conference on Circuits and Systems (ICCS), 64-67, 2020
2020
Investigation of Temperature and Source/Drain Overlap Impact on Negative Capacitance Silicon Nanotube FET (NC Si NTFET) with Sub-60mV/decade Switching
S Moparthi, PK Tiwari, VR Samoju, GK Saramekala
IEEE Transactions on Nanotechnology 19, 800-806, 2020
2020
Communications (AE▄)
S Moparthi, KP Adarsh, PK Tiwari, GK Saramekala
2020
Temperature Dependence of Subthreshold Characteristics of Negative Capacitance Recessed-Source/Drain (NC RS/D) SOI MOSFET
S Moparthi, PK Tiwari, VR Samoju, GK Saramekala
2019 IEEE International Symposium on Smart Electronic Systems (iSESá…, 2019
2019
Modeling of Drain current and analog characteristics of dual-metal quadruple gate (DMQG) MOSFETs
VR Samoju, GK Saramekala, PK Tiwari, AK Swain, K Mahapatra
2019 IEEE International Symposium on Smart Electronic Systems (iSESá…, 2019
2019
Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control
GK Saramekala, PK Tiwari
Journal of Electronic Materials 46 (8), 5046-5056, 2017
2017
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Articles 1–20