| An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs S Dubey, A Santra, G Saramekala, M Kumar, PK Tiwari IEEE Transactions on Nanotechnology 12 (5), 766-774, 2013 | 57 | 2013 |
| An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET GK Saramekala, A Santra, S Dubey, S Jit, PK Tiwari Superlattices and Microstructures 60, 580-595, 2013 | 24 | 2013 |
| Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs GK Saramekala, A Santra, M Kumar, S Dubey, S Jit, PK Tiwari Journal of Computational Electronics 13, 467-476, 2014 | 15 | 2014 |
| Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates PK Tiwari, GK Saramekala, S Dubey, AK Mukhopadhyay Journal of Semiconductors 35 (10), 104002, 2014 | 14 | 2014 |
| An analytical surface potential modeling of fully-depleted symmetrical double-gate (DG) strained-Si MOSFETs including the effect of interface charges S Sarangi, A Santra, S Bhushan, KS Gopi, S Dubey, PK Tiwari 2013 Students Conference on Engineering and Systems (SCES), 1-5, 2013 | 12 | 2013 |
| Investigation of temperature and source/drain overlap impact on negative capacitance silicon nanotube FET (NC Si NTFET) with sub-60mV/decade switching S Moparthi, PK Tiwari, VR Samoju, GK Saramekala IEEE Transactions on Nanotechnology 19, 800-806, 2020 | 9 | 2020 |
| Analog and RF performance evaluation of negative capacitance SOI junctionless transistor S Moparthi, KP Adarsh, PK Tiwari, GK Saramekala AEU-International Journal of Electronics and Communications 122, 153243, 2020 | 9 | 2020 |
| Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs PK Tiwari, M Kumar, RS Naik, GK Saramekala Journal of Semiconductors 37 (6), 064003, 2016 | 7 | 2016 |
| Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs GK Saramekala, S Dubey, PK Tiwari Superlattices and Microstructures 76, 77-89, 2014 | 7 | 2014 |
| A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric GK Saramekala, S Dubey, PK Tiwari Chinese Physics B 24 (10), 108505, 2015 | 6 | 2015 |
| Sensitivity analysis of silicon nanotube FET (Si NTFET) with TCAD assisted machine learning S Moparthi, PK Tiwari, GK Saramekala Silicon 14 (14), 9021-9031, 2022 | 5 | 2022 |
| Automated Seed Sowing Agribot YN Kumar, C Haswanth, MH Kiran, MK Rao, R Raj, GK Saramekala, ... 2019 IEEE 1st International Conference on Energy, Systems and Information …, 2019 | 4 | 2019 |
| Genetic algorithm-based threshold voltage prediction of SOI JLT using multi-variable nonlinear regression S Moparthi, PK Tiwari, GK Saramekala 2021 International Symposium on Devices, Circuits and Systems (ISDCS), 1-4, 2021 | 3 | 2021 |
| Analog/RF performance of triple material gate stack-graded channel double gate-junctionless strained-silicon MOSFET with Fixed Charges SS Rao, RDB Joseph, VD Chintala, GK Saramekala, D Srikar, NB Rao Silicon, 1-14, 2021 | 3 | 2021 |
| Machine learning based device simulation using multi-variable non-linear regression to assess the impact of device parameter variability on threshold voltage of double gate-all … S Moparthi, C Yadav, GK Saramekala, PK Tiwari 2020 IEEE 2nd International Conference on Circuits and Systems (ICCS), 64-67, 2020 | 3 | 2020 |
| Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO2|La2O3|HfO2 (HLH) Sandwich Gate … L Ramesh, S Moparthi, PK Tiwari, VR Samoju, GK Saramekala Semiconductors 54, 1290-1295, 2020 | 3 | 2020 |
| Temperature dependence of subthreshold characteristics of negative capacitance recessed-source/drain (NC RS/D) SOI MOSFET S Moparthi, PK Tiwari, VR Samoju, GK Saramekala 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 3 | 2019 |
| An analytical threshold voltage model of fully depleted (FD) recessed-source/drain (re-S/D) SOI MOSFETs with Back-gate control GK Saramekala, PK Tiwari Journal of Electronic Materials 45, 5367-5374, 2016 | 3 | 2016 |
| A simulation-based study of gate misalignment effects in triple-material double-gate (tmdg) mosfets S Sarangi, S Bhushan, SG Krishna, A Santra, PK Tiwari 2013 International Mutli-Conference on Automation, Computing, Communication …, 2013 | 3 | 2013 |
| Numerical simulation based study of analog and RF performance of a Re-S/D SOI MOSFETs G krishna Saramekala, S Dubey, P kumar Tiwari Supperlattices and Microstructures Journal 76, 77-89, 2014 | 2 | 2014 |
Pramod Kumar TiwariIndian Institute of Technology PatnaVerified email at iitp.ac.in
