Dr. Gopi Krishna Saramekala
Dr. Gopi Krishna Saramekala
Verified email at nitc.ac.in
TitleCited byYear
An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs
S Dubey, A Santra, G Saramekala, M Kumar, PK Tiwari
IEEE Transactions on Nanotechnology 12 (5), 766-774, 2013
302013
An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET
GK Saramekala, A Santra, S Dubey, S Jit, PK Tiwari
Superlattices and Microstructures 60, 580-595, 2013
132013
Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs
GK Saramekala, A Santra, M Kumar, S Dubey, S Jit, PK Tiwari
Journal of Computational Electronics 13 (2), 467-476, 2014
102014
Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates
PK Tiwari, GK Saramekala, S Dubey, AK Mukhopadhyay
Journal of Semiconductors 35 (10), 104002, 2014
52014
A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric
GK Saramekala, S Dubey, PK Tiwari
Chinese Physics B 24 (10), 108505, 2015
42015
Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs
GK Saramekala, S Dubey, PK Tiwari
Superlattices and Microstructures 76, 77-89, 2014
32014
An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control
GK Saramekala, PK Tiwari
Journal of Electronic Materials 45 (10), 5367-5374, 2016
12016
A Two-Dimensional Subthreshold Current Model of Recessed-Source/Drain (Re-S/D) SOI MOSFETs with High-k Dielectric
GK Saramekala, PK Tiwari
2014 8th Asia Modelling Symposium, 258-263, 2014
12014
ATLAS™ based simulation study of the electrical characteristics of dual-metal-gate (DMG) fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs
GK Saramekala, S Jit, PK Tiwari
2014 International Conference on Advances in Electrical Engineering (ICAEE), 1-4, 2014
12014
Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control
GK Saramekala, PK Tiwari
Journal of Electronic Materials 46 (8), 5046-5056, 2017
2017
Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs
GK Saramekala
2017
Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs
PK Tiwari, M Kumar, RS Naik, GK Saramekala
Journal of Semiconductors 37 (6), 064003, 2016
2016
A Ballistic Subthreshold Current Model for Ultra-Short Channel Recessed-Source/Drain (Re-S/D) SOI MOSFETs
GK Saramekala, PK Tiwari
Journal of Nanoengineering and Nanomanufacturing 5 (2), 141-145, 2015
2015
Threshold Voltage Modeling of Recessed Source/Drain Soi Mosfet with Vertical Gaussian Doping Profile
MK Kushwaha
2015
Virtual Fabrication of Short-Channel RecessedSource/Drain (Re-S/D) SOI MOSFETs
S Dasari, GK Saramekala, PK Tiwari
2015
An analytical subthreshold surface potential model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET
GK Saramekala, PK Tiwari, S Jit
2013
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