| Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability S Saha, RS Chakraborty, SS Nuthakki, Anshul, D Mukhopadhyay Cryptographic Hardware and Embedded Systems--CHES 2015: 17th International …, 2015 | 130 | 2015 |
| Anshul, and D. Mukhopadhyay. Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability S Saha, RS Chakraborty, SS Nuthakki International Workshop on Cryptographic Hardware and Embedded Systems (CHES …, 2015 | 47 | 2015 |
| Symbolic quick error detection using symbolic initial state for pre-silicon verification MR Fadiheh, J Urdahl, SS Nuthakki, S Mitra, C Barrett, D Stoffel, W Kunz 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2018 | 24 | 2018 |
| Optimization of the IEEE 1687 access network for hybrid access schedules SS Nuthakki, R Karmakar, S Chattopadhyay, K Chakrabarty 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 17 | 2016 |
| Unlocking the power of formal hardware verification with cosa and symbolic qed F Lonsing, K Ganesan, M Mann, SS Nuthakki, E Singh, M Srouji, Y Yang, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 9 | 2019 |
| Effective pre-silicon verification of processor cores by breaking the bounds of symbolic quick error detection K Ganesan, F Lonsing, SS Nuthakki, E Singh, MR Fadiheh, W Kunz, ... arXiv preprint arXiv:2106.10392, 2021 | 4 | 2021 |
| Integrated circuit chip with cores asymmetrically oriented with respect to each other JS Nayyar, SS Nuthakki, R Gulati, A Shrimali US Patent 10,002,056, 2018 | 4 | 2018 |
| Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other JS Nayyar, SS Nuthakki, R Gulati, A Shrimali US Patent App. 18/323,931, 2023 | 1 | 2023 |
| Integrated circuit chip with cores asymmetrically oriented with respect to each other JS Nayyar, SS Nuthakki, R Gulati, A Shrimali US Patent 11,698,841, 2023 | 1 | 2023 |
| Integrated circuit chip with cores asymmetrically oriented with respect to each other JS Nayyar, SS Nuthakki, R Gulati, A Shrimali US Patent 10,649,865, 2020 | 1 | 2020 |
| Test set customization for improved fault diagnosis without sacrificing coverage SS Nuthakki, S Chattopadhyay, M Chakraborty 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1574-1577, 2015 | 1 | 2015 |
| Integrated circuit chip with cores asymmetrically oriented with respect to each other JS Nayyar, SS Nuthakki, R Gulati, A Shrimali US Patent 11,269,742, 2022 | | 2022 |
| Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores K Ganesan, SS Nuthakki arXiv preprint arXiv:1908.06757, 2019 | | 2019 |
| Integrated circuit chip with cores asymmetrically oriented with respect to each other AS Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati US Patent US10002056B2, 2018 | | 2018 |
| Integrated circuit chip with cores asymmetrically oriented with respect to each other JS Nayyar, SS Nuthakki, R Gulati, A Shrimali US Patent 10,002,056, 2018 | | 2018 |
| An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets SS Nuthakki, S Chattopadhyay 2015 IEEE 24th Asian Test Symposium (ATS), 151-156, 2015 | | 2015 |
| Tutorial T2E: Pre-Silicon Verification and Post-Silicon Validation: Dramatic Improvements through Disruptive Innovations S Mitra, SS Nuthakki, E Singh | | |
