| An 8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS D Anh-Tuan, JYS Low, JYL Low, ZH Kong, X Tan, KS Yeo IEEE Transactions on Circuits and Systems I: Regular Papers 58 (6), 1252-1263, 2011 | 118 | 2011 |
| Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement B Wang, TQ Nguyen, AT Do, J Zhou, M Je, TTH Kim IEEE Transactions on Circuits and Systems I: Regular Papers 62 (2), 441-448, 2014 | 104 | 2014 |
| Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM AT Do, ZH Kong, KS Yeo, JYS Low IEEE transactions on very large scale integration (VLSI) systems 19 (2), 196-204, 2009 | 79 | 2009 |
| A high speed low power CAM with a parity bit and power-gated ML sensing AT Do, S Chen, ZH Kong, KS Yeo IEEE Transactions on very large scale integration (VLSI) systems 21 (1), 151-156, 2012 | 76 | 2012 |
| 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance AT Do, C Yin, K Velayudhan, ZC Lee, KS Yeo, TTH Kim IEEE Journal of Solid-State Circuits 49 (7), 1487-1498, 2014 | 55 | 2014 |
| Development of a miniaturized stimulation device for electrical stimulation of cells GM Xiong, AT Do, JK Wang, CL Yeoh, KS Yeo, C Choong Journal of biological engineering 9, 1-10, 2015 | 44 | 2015 |
| A wireless multi-channel peripheral nerve signal acquisition system-on-chip KA Ng, C Yuan, A Rusly, AT Do, B Zhao, SC Liu, WYX Peh, XY Thow, ... IEEE Journal of Solid-State Circuits 54 (8), 2266-2280, 2019 | 43 | 2019 |
| An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With W/Channel in 65-nm CMOS AT Do, SMA Zeinolabedin, D Jeon, D Sylvester, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 126-137, 2018 | 41 | 2018 |
| “Click” xylosides initiate glycosaminoglycan biosynthesis in a mammalian cell line B Kuberan, M Ethirajan, XV Victor, V Tran, K Nguyen, A Do ChemBioChem 9 (2), 198-200, 2008 | 38 | 2008 |
| Type 2 diabetes is associated with higher trabecular bone density but lower cortical bone density: the Vietnam Osteoporosis Study LT Ho-Pham, PMN Chau, AT Do, HC Nguyen, TV Nguyen Osteoporosis International 29, 2059-2067, 2018 | 36 | 2018 |
| Hybrid-mode SRAM sense amplifiers: New approach on transistor sizing D Anh-Tuan, K Zhi-Hui, Y Kiat-Seng IEEE Transactions on Circuits and Systems II: Express Briefs 55 (10), 986-990, 2008 | 36 | 2008 |
| Imparting electroactivity to polycaprolactone fibers with heparin-doped polypyrrole: modulation of hemocompatibility and inflammatory responses GM Xiong, S Yuan, JK Wang, AT Do, NS Tan, KS Yeo, C Choong Acta Biomaterialia 23, 240-249, 2015 | 35 | 2015 |
| 0.2 V 8T SRAM with PVT-aware bitline sensing and column-based data randomization AT Do, ZC Lee, B Wang, IJ Chang, X Liu, TTH Kim IEEE Journal of Solid-State Circuits 51 (6), 1487-1498, 2016 | 30 | 2016 |
| Design of a power-efficient CAM using automated background checking scheme for small match line swing AT Do, C Yin, KS Yeo, TTH Kim 2013 Proceedings of the ESSCIRC (ESSCIRC), 209-212, 2013 | 29 | 2013 |
| Antidiabetic and antioxidant activities of red seaweed Laurencia dendroidea TH Nguyen, TLP Nguyen, TVA Tran, AD Do, SM Kim Asian Pacific Journal of Tropical Biomedicine 9 (12), 501-509, 2019 | 28 | 2019 |
| A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2per channel in 65-nm CMOS SMA Zeinolabedin, AT Do, D Jeon, D Sylvester, TTH Kim 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 28 | 2016 |
| A low-power CAM with efficient power and delay trade-off AT Do, S Chen, ZH Kong, KS Yeo 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2573-2576, 2011 | 26 | 2011 |
| Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency L Yang, H Zhang, T Luo, C Qu, MTL Aung, Y Cui, J Zhou, MM Wong, J Pu, ... Neurocomputing 474, 128-140, 2022 | 25 | 2022 |
| A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router J Pu, WL Goh, VP Nambiar, MM Wong, AT Do IEEE Transactions on Circuits and Systems I: Regular Papers 68 (12), 5081-5094, 2021 | 24 | 2021 |
| Criterion to evaluate input-offset voltage of a latch-type sense amplifier AT Do, ZH Kong, KS Yeo IEEE Transactions on Circuits and Systems I: Regular Papers 57 (1), 83-92, 2009 | 22 | 2009 |
Tony Tae-Hyoung KIMAssociate Professor, Nanyang Technological UniversityVerified email at ntu.edu.sg
