Lavanya Subramanian
Lavanya Subramanian
Silicon Performance Architect, Facebook Reality Labs
Verified email at oculus.com
Title
Cited by
Cited by
Year
Reducing memory interference in multicore systems via application-aware memory channel partitioning
SP Muralidhara, L Subramanian, O Mutlu, M Kandemir, T Moscibroda
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
2752011
Staged memory scheduling: achieving high performance and scalability in heterogeneous systems
R Ausavarungnirun, KKW Chang, L Subramanian, GH Loh, O Mutlu
ACM SIGARCH Computer Architecture News 40 (3), 416-427, 2012
2482012
Tiered-latency DRAM: A low latency and low cost DRAM architecture
D Lee, Y Kim, V Seshadri, J Liu, L Subramanian, O Mutlu
High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th …, 2013
2472013
MISE: Providing performance predictability and improving fairness in shared main memory systems
L Subramanian, V Seshadri, Y Kim, B Jaiyen, O Mutlu
High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th …, 2013
1592013
Research problems and opportunities in memory systems
O Mutlu, L Subramanian
Supercomputing frontiers and innovations 1 (3), 19, 2014
1422014
The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory
L Subramanian, V Seshadri, A Ghosh, S Khan, O Mutlu
Proceedings of the 48th International Symposium on Microarchitecture, 62-75, 2015
1382015
DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators
H Usui, L Subramanian, KKW Chang, O Mutlu
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 65, 2016
982016
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM
D Lee, L Subramanian, R Ausavarungnirun, J Choi, O Mutlu
Parallel Architecture and Compilation (PACT), 2015 International Conference …, 2015
972015
The blacklisting memory scheduler: Achieving high performance and fairness at low cost
L Subramanian, D Lee, V Seshadri, H Rastogi, O Mutlu
Computer Design (ICCD), 2014 32nd IEEE International Conference on, 8-15, 2014
942014
Design-induced latency variation in modern dram chips: Characterization, analysis, and latency reduction mechanisms
D Lee, S Khan, L Subramanian, S Ghose, R Ausavarungnirun, ...
Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017
792017
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
D Lee, S Khanℵ, L Subramanian, S Ghose, R Ausavarungnirun, ...
79*
BLISS: Balancing performance, fairness and complexity in memory access scheduling
L Subramanian, D Lee, V Seshadri, H Rastogi, O Mutlu
IEEE Transactions on Parallel and Distributed Systems 27 (10), 3071-3087, 2016
592016
A-DRM: Architecture-aware distributed resource management of virtualized clusters
H Wang, C Isci, L Subramanian, J Choi, D Qian, O Mutlu
ACM SIGPLAN Notices 50 (7), 93-106, 2015
312015
Systems and methods for page management using local page information
S Srikanth, L Subramanian, S Subramoney
US Patent App. 10/191,689, 2019
20*2019
GrandSLAm: Guaranteeing SLAs for Jobs in Microservices Execution Frameworks
RS Kannan, L Subramanian, A Raju, J Ahn, J Mars, L Tang
Proceedings of the Fourteenth EuroSys Conference 2019, 34, 2019
172019
Scoreboard approach to managing idle page close timeout duration in memory
S Srikanth, L Subramanian, S Subramoney
US Patent App. 10/176,124, 2019
17*2019
The main memory system: Challenges and opportunities
O Mutlu, J Meza, L Subramanian
Communications of the Korean Institute of Information Scientists and Engineers, 2015
162015
Reducing DRAM latency by exploiting design-induced latency variation in modern DRAM chips
D Lee, S Khan, L Subramanian, R Ausavarungnirun, G Pekhimenko, ...
arXiv preprint arXiv:1610.09604, 2016
152016
SQUASH: Simple QoS-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators
H Usui, L Subramanian, K Chang, O Mutlu
arXiv preprint arXiv:1505.07502, 2015
142015
The blacklisting memory scheduler: Balancing performance, fairness and complexity
L Subramanian, D Lee, V Seshadri, H Rastogi, O Mutlu
IEEE, 2015
102015
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