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Arunachalam V
Arunachalam V
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Year
Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications
V Arunachalam, A Noel Joseph Raj
IET Circuits, Devices & Systems 8 (6), 526-531, 2014
292014
An integrated feature frame work for automated segmentation of COVID‐19 infection from lung CT images
D Selvaraj, A Venkatesan, VGV Mahesh, AN Joseph Raj
International Journal of Imaging Systems and Technology 31 (1), 28-46, 2021
182021
Architectural Analysis of RSA cryptosystem on FPGA
V Garg, V Arunachalam
International Journal of Computer Applications 26 (8), 30-34, 2011
82011
Efficient dual-precision floating-point fused-multiply-add architecture
V Arunachalam, ANJ Raj, N Hampannavar, CB Bidul
Microprocessors and Microsystems 57, 23-31, 2018
72018
FPGA implementation & comparison of current trends in memory scheduler for multimedia application
AM Kulkarni, V Arunachalam
Proceedings of the International Conference & Workshop on Emerging Trends in…, 2011
22011
Hardware/software partitioning algorithm for embedded systems with repeated functionalities
V Arunachalam, S Sapra, NSK Chaitanya, JP Rainac
TENCON 2008-2008 IEEE Region 10 Conference, 1-6, 2008
22008
Performance improvement of vector-radix decimation-in-frequency 3D-DCT/IDCT using variable word length
V Arunachalam, AN Joseph Raj, S Deepika
Circuits, Systems, and Signal Processing 40 (4), 1818-1831, 2021
12021
Power domain, physical aware scan chain allocation and reordering
V Divakar, D., Arunachalam
Indian Journal of Science and Technology, 2016
12016
Fusion of near-infrared and RGB images on a FPGA using high level synthesis tool
ANJ Raj, M Murugappan, V Arunachalam
Journal of Engineering Research 9 (3A), 2021
2021
Microelectronic Devices, Circuits and Systems: Second International Conference, ICMDCS 2021, Vellore, India, February 11-13, 2021, Revised Selected Papers
V Arunachalam, K Sivasankaran
Springer Nature, 2021
2021
Analysis & Design of Convolution Operator for High Speed and High Accuracy Convolutional Neural Network-Based Inference Engines
S Deepika, V Arunachalam
IEEE Transactions on Computers 71 (2), 390-396, 2021
2021
Memory Efficient ASIC Implementation of Line Hough Transform
KV Pachkor, V Arunachalam
2018 3rd IEEE International Conference on Recent Trends in Electronics…, 2018
2018
DESIGN OF 8 8 2D-DCT PROCESSOR FOR HIGH ACCURACY HIGH PERFORMANCE APPLICATIONS
V Arunachalam, ANJ Raj
Far East Journal of Electronics and Communications 15 (2), 151, 2015
2015
Vibhor Garg
V Arunachalam
2011
Risperidone alone versus risperidone and citalopram in patients with neuroleptic-naive, recent-onset schizophrenia: a randomized double-blind study
JP John, V Arunachalam, R Bhuvaneshwari, CC Lopez, S Prabhu, ...
AUSTRALIAN AND NEW ZEALAND JOURNAL OF PSYCHIATRY 40, A140-A140, 2006
2006
FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H. 264/AVC Application
AM Kulkarni, V Arunachalam
Design of High Gain Sigma Delta Modulator for Digital Communication Applications
BS Abhinav, NN Paul, SB Kumar, V Arunachalam
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