| Fantastic4: A hardware-software co-design approach for efficiently running 4bit-compact multilayer perceptrons S Wiedemann, S Shivapakash, D Becking, P Wiedemann, W Samek, ... IEEE Open Journal of Circuits and Systems 2, 407-419, 2021 | 10 | 2021 |
| A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks S Shivapakash, H Jain, O Hellwich, F Gerfers IEEE Open Journal of Circuits and Systems 2, 156-169, 2021 | 9 | 2021 |
| A power efficient multi-bit accelerator for memory prohibitive deep neural networks S Shivapakash, H Jain, O Hellwich, F Gerfers 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 9 | 2020 |
| HsClone genetic algorithm implementation on a combinational circuit S Suhas, G Malhotra, VH Rajini IETE Journal of Research 69 (3), 1373-1381, 2023 | 6 | 2023 |
| A 9-bit, 45mW, 0.05mm2 Source-Series-Terminated DAC Driver with Echo Canceller in 22nm CMOS for In-Vehicle Communication H Ghafarian, S Shivapakash, S Mortazavi, P Scholz, N Lotfi, F Gerfers IEEE Solid State Circuit Letters, 2021 | 5 | 2021 |
| Energy efficient hardware architectures for memory prohibitive deep neural networks S Shivapakash | | 2024 |
| Implementation of 2-Bit Multiplier Using HsClone Genetic Algorithm S Suhas, G Malhotra, VH Rajini IETE Journal of Research, 2020 | | 2020 |
| Comparison of Hsclone and Roulette Genetic Algorithms on the Application of Combinational Circuits S Suhas, G Malhotra, VH Rajini International Journal of Engineering and Advanced Technology (IJEAT) 5 (4), 2016 | | 2016 |
