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Chester Rebeiro
Chester Rebeiro
Indian Institute of Technology Madras
Verified email at cs.columbia.edu - Homepage
Title
Cited by
Cited by
Year
Bitslice implementation of AES
C Rebeiro, D Selvakumar, ASL Devi
International Conference on Cryptology and Network Security, 203-212, 2006
1002006
Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs
C Rebeiro, SS Roy, D Mukhopadhyay
International Workshop on Cryptographic Hardware and Embedded Systems, 494-511, 2012
802012
High speed compact elliptic curve cryptoprocessor for FPGA platforms
C Rebeiro, D Mukhopadhyay
International Conference on Cryptology in India, 376-388, 2008
622008
Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed
SS Roy, C Rebeiro, D Mukhopadhyay
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (5), 901-909, 2012
592012
Shakti-t: A risc-v processor with light weight security extensions
A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan
Proceedings of the Hardware and Architectural Support for Security and …, 2017
472017
Revisiting the Itoh-Tsujii inversion algorithm for FPGA platforms
C Rebeiro, SS Roy, DS Reddy, D Mukhopadhyay
IEEE Transactions on very large scale integration (vlsi) systems 19 (8 …, 2010
462010
XFC: a framework for exploitable fault characterization in block ciphers
P Khanna, C Rebeiro, A Hazra
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
342017
Cache timing attacks on Clefia
C Rebeiro, D Mukhopadhyay, J Takahashi, T Fukunaga
International conference on cryptology in India, 104-118, 2009
332009
Timing channels in cryptography: a micro-architectural perspective
C Rebeiro, D Mukhopadhyay, S Bhattacharya
Springer, 2014
302014
Power attack resistant efficient FPGA architecture for Karatsuba multiplier
C Rebeiro, D Mukhopadhyay
21st International Conference on VLSI Design (VLSID 2008), 706-711, 2008
292008
Theoretical modeling of the Itoh-Tsujii inversion algorithm for enhanced performance on k-LUT based FPGAs
SS Roy, C Rebeiro, D Mukhopadhyay
2011 Design, Automation & Test in Europe, 1-6, 2011
272011
Cryptanalysis of CLEFIA using differential methods with cache trace patterns
C Rebeiro, D Mukhopadhyay
Cryptographers’ track at the RSA conference, 89-103, 2011
252011
Pinpointing cache timing attacks on AES
C Rebeiro, M Mondal, D Mukhopadhyay
2010 23rd International Conference on VLSI Design, 306-311, 2010
252010
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER
R Bodduna, V Ganesan, P Slpsk, K Veezhinathan, C Rebeiro
IEEE Computer Architecture Letters 19 (1), 9-12, 2020
242020
Boosting profiled cache timing attacks with a priori analysis
C Rebeiro, D Mukhopadhyay
IEEE Transactions on Information Forensics and Security 7 (6), 1900-1905, 2012
222012
PERI: A configurable posit enabled risc-V core
S Tiwari, N Gala, C Rebeiro, V Kamakoti
ACM Transactions on Architecture and Code Optimization (TACO) 18 (3), 1-26, 2021
21*2021
DRECON: DPA resistant encryption by construction
S Hajra, C Rebeiro, S Bhasin, G Bajaj, S Sharma, S Guilley, ...
International Conference on Cryptology in Africa, 420-439, 2014
212014
PARAM: A microprocessor hardened for power side-channel attack resistance
MA KF, V Ganesan, R Bodduna, C Rebeiro
2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020
202020
Hardware prefetchers leak: A revisit of SVF for cache-timing attacks
S Bhattacharya, C Rebeiro, D Mukhopadhyay
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture …, 2012
202012
Karna: A gate-sizing based security aware EDA flow for improved power side-channel attack protection
P Slpsk, PK Vairam, C Rebeiro, V Kamakoti
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
192019
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