Follow
Subodh Wairya
Subodh Wairya
Professor EC Deptt Institute of Engineering & Technology, Lucknow
Verified email at ietlucknow.ac.in
Title
Cited by
Cited by
Year
Design analysis of XOR (4T) based low voltage CMOS full adder circuit
S Wairya, G Singh, RK Nagaria, S Tiwari
2011 Nirma University International Conference on Engineering, 1-7, 2011
732011
Hybrid deep neural network with adaptive galactic swarm optimization for text extraction from scene images
D Pandey, BK Pandey, S Wairya
Soft Computing 25 (2), 1563-1580, 2021
702021
Comparative performance analysis of XORXNOR function based high-speed CMOS full adder circuits for low voltage VLSI design
S Wairya, RK Nagaria, S Tiwari
International Journal of VLSI Design & Communication Systems 3 (2), 221, 2012
672012
Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design
S Wairya, RK Nagaria, S Tiwari
VLSI Design 2012 (1), 173079, 2012
662012
Application of integrated steganography and image compressing techniques for confidential information transmission
BK Pandey, D Pandey, S Wairya, G Agarwal, P Dadeech, SR Dogiwal, ...
Cyber security and network security, 169-191, 2022
552022
Prediction of breast cancer using extremely randomized clustering forests (ERCF) technique: prediction of breast cancer
A Gupta, R Anand, D Pandey, N Sindhwani, S Wairya, BK Pandey, ...
International Journal of Distributed Systems and Technologies (IJDST) 12 (4 …, 2021
502021
New design methodologies for high speed low power XOR-XNOR circuits
SS Mishra, S Wairya, RK Nagaria, S Tiwari
World Academy of Science, Engineering and Technology 55, 200-206, 2009
452009
New Design Methodologies for High-Speed Mixed Mode CMOS Full Adder Circuits
S Wairya, RK Nagaria, S Tiwari
International Journal of VLSI Design & Communication Systems 2 (2), 78-98, 2011
432011
Deep learning and particle swarm optimisation-based techniques for visually impaired humans' text recognition and identification
BK Pandey, D Pandey, S Wariya, G Aggarwal, R Rastogi
Augmented Human Research 6 (1), 14, 2021
402021
Design of conservative, reversible sequential logic for cost efficient emerging nano circuits with enhanced testability
NK Misra, S Wairya, B Sen
Ain Shams Engineering Journal 9 (4), 2027-2037, 2018
382018
A new mixed gate diffusion input full adder topology for high speed low power digital circuits
AK Agrawal, S Wairya, RK Nagaria, S Tiwari
World Applied Science Journal 7, 138-144, 2009
352009
An approach for object tracking, categorization, and autopilot guidance for passive homing missiles
D Pandey, S Wairya, M Sharma, AK Gupta, R Kakkar, BK Pandey
Aerospace Systems 5 (4), 553-566, 2022
342022
A deep neural network-based approach for extracting textual images from deteriorate images
BK Pandey, D Pandey, S Wariya, G Agarwal
EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 8 …, 2021
322021
Secret data transmission using advanced steganography and image compression
D Pandey, S Wairya, RS Al Mahdawi, SAM Najim, HA Khalaf, ...
International Journal of Nonlinear Analysis and Applications 12 (Special …, 2021
302021
An advanced morphological component analysis, steganography, and deep learning-based system to transmit secure textual data
BK Pandey, D Pandey, S Wairya, G Agarwal
International Journal of Distributed Artificial Intelligence (IJDAI) 13 (2 …, 2021
292021
Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits
NK Misra, B Sen, S Wairya
Journal of Computational Electronics 16 (2), 442-458, 2017
272017
New design methodologies for high-speed low-voltage 1 bit CMOS Full Adder circuits
S Wairya, RK Nagaria, S Tiwari
International Journal of Computer Technology and Application 2 (3), 190-198, 2011
262011
Testable novel parity-preserving reversible gate and low-cost quantum decoder design in 1D molecular-QCA
NK Misra, B Sen, S Wairya, B Bhoi
Journal of Circuits, Systems and Computers 26 (09), 1750145, 2017
252017
Novel lossless grounded and floating inductance simulators employing a grounded capacitor based on CC-CFA
A Singh, MK Jain, S Wairya
Journal of Circuits, Systems and Computers 28 (06), 1950093, 2019
242019
Modular Design of 2n:1 Quantum Dot Cellular Automata Multiplexers and its Application, via Clock Zone based Crossover.
S Singh, S Pandey, S Wairya
International Journal of Modern Education & Computer Science 8 (7), 2016
242016
The system can't perform the operation now. Try again later.
Articles 1–20