| New low-power techniques: leakage feedback with stack & sleep stack with keeper PK Pal, RS Rathore, AK Rana, G Saini 2010 International Conference on Computer and Communication Technology …, 2010 | 32 | 2010 |
| Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design RS Rathore, AK Rana Superlattices and Microstructures 110, 68-81, 2017 | 20 | 2017 |
| Impact of high-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET R Sharma, RS Rathore, AK Rana Journal of Circuits, Systems and Computers 27 (04), 1850063, 2018 | 14 | 2018 |
| Line edge roughness induced threshold voltage variability in nano-scale FinFETs RS Rathore, R Sharma, AK Rana Superlattices and Microstructures 103, 304-313, 2017 | 13 | 2017 |
| Impact of line edge roughness on the performance of 14-nm FinFET: device-circuit co-design RS Rathore, AK Rana Superlattices and Microstructures 113, 213-227, 2018 | 9 | 2018 |
| Threshold voltage variability induced by statistical parameters fluctuations in nanoscale bulk and SOI FinFETs RS Rathore, AK Rana, R Sharma 2017 4th International Conference on Signal Processing, Computing and …, 2017 | 9 | 2017 |
| Effect of metal gate work function variation on underlap FinFET RS Rathore, VM Srivastava 2022 45th International Spring Seminar on Electronics Technology (ISSE), 1-5, 2022 | 6 | 2022 |
| Impact of work function fluctuations on threshold voltage variability in a nanoscale FinFETs RS Rathore, R Sharma, AK Rana 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 5 | 2016 |
| Performance analysis of CNTs as an application for future VLSI interconnects S Sharma, PKP Rajeevan Chandel, RS Rathore Microelectronics and Solid State Electronics 1 (3), 69-73, 2012 | 4 | 2012 |
| Device-and circuit-level variability due to random discrete dopant in resist-and spacer-defined nanoscale FinFETs RS Rathore, AK Rana Journal of Micro/Nanolithography, MEMS, and MOEMS 17 (1), 013507-013507, 2018 | 3 | 2018 |
| Nanoscale static random-access-memory design using strained underlap ultra thin silicon on insulator MOSFET for improved performance R Sharma, RS Rathore, AK Rana Journal of nanoelectronics and optoelectronics 12 (4), 359-364, 2017 | 3 | 2017 |
| Impact of oxide thickness fluctuation for resist-and spacer-defined FinFETs RS Rathore, AK Rana, VM Srivastava 2022 IEEE Latin American Electron Devices Conference (LAEDC), 1-4, 2022 | 1 | 2022 |
| Threshold voltage variability induced by spacer-and resist-defined patterning techniques in nanoscale FinFETs RS Rathore, R Sharma, AK Rana Journal of Micro/Nanolithography, MEMS, and MOEMS 16 (1), 013503-013503, 2017 | 1 | 2017 |
| (Digital Presentation) Influence of Fin Width Modulation on Nanoscale FinFET RS Rathore, VM Srivastava ECS Transactions 109 (7), 11, 2022 | | 2022 |
| Regression Analysis of Static Noise Margin and Transconductance for Underlap Lengths of FinFET RS Rathore, VM Srivastava 2022 45th International Spring Seminar on Electronics Technology (ISSE), 1-5, 2022 | | 2022 |
| Effect of Multi-fin with Independent LER on Intrinsic Statistical Variability Sources RS Rathore, VM Srivastava | | |
Ashwani Kumar RanaAssociate Professor, NIT HamirpurVerified email at nith.ac.in
