|Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer|
GJ Hinton, DB Papworth, AF Glew, MA Fetterman, RP Colwell
US Patent 5,721,855, 1998
|MLP yes! ILP no|
ASPLOS Wild and Crazy Idea Session 98, 1998
|Authenticated code module|
AF Glew, JA Sutton, LO Smith, DW Grawrock, G Neiger, MA Kozuch
US Patent 7,308,576, 2007
|Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner|
D Lin, RR Vakkalagadda, AF Glew, LM Mennemeier, AD Peleg, D Bistry, ...
US Patent 5,852,726, 1998
|Methods and systems to control virtual machines|
SM Bennett, G Neiger, EC Cota-Robles, S Jeyasingh, A Kagi, MA Kozuch, ...
US Patent 7,318,141, 2008
|Processor supporting execution of an authenticated code instruction|
A Glew, J Sutton, L Smith, D Grawrock, G Neiger, M Kozuch
US Patent App. 10/039,961, 2003
|Method and apparatus for handling speculative memory access operations|
AF Glew, H Akkary
US Patent 5,956,753, 1999
AF Glew, DA Gerrity, CT Tegreene
US Patent 8,930,714, 2015
|System and method for protection against untrusted system management code by redirecting a system management interrupt and creating a virtual machine container|
J Sutton, D Grawrock, R Uhlig, D Poisner, A Glew, C Hall, L Smith, ...
US Patent App. 10/165,597, 2003
|Fault-tolerant boot strap mechanism for a multiprocessor system|
M Karnik, J Batz, K Tiruvallur, A Glew, F Binns, S Thakkar, N Sarangdhar
US Patent 5,724,527, 1998
|Method and apparatus for processing memory-type information within a microprocessor|
AF Glew, GJ Hinton
US Patent 5,751,996, 1998
|Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations|
JM Abramson, DB Papworth, HH Akkary, AF Glew, GJ Hinton, ...
US Patent 5,751,983, 1998
AF Glew, DA Gerrity, CT Tegreene
US Patent 9,575,903, 2017
|Method and apparatus for implementing a single clock cycle line replacement in a data cache unit|
H Akkary, MS Joshi, R Murray, BE Lince, PD Madland, AF Glew, ...
US Patent 5,526,510, 1996
|System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time|
G Neiger, SM Bennett, E Cota-Robles, S Schoenberg, CD Hall, ...
US Patent 7,840,962, 2010
|Apparatus and method for handling string operations in a pipelined processor|
DB Papworth, MA Fetterman, AF Glew, LO Smith III, MM Hancock, ...
US Patent 5,404,473, 1995
|Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history|
BD Hoyt, GJ Hinton, AF Glew, S Natarajan
US Patent 5,584,001, 1996
|Method and apparatus for blocking execution of and storing load operations during their execution|
JM Abramson, H Akkary, AF Glew, GJ Hinton, KG Konigsfeld, PD Madland
US Patent 5,881,262, 1999
|Method and apparatus for dynamic allocation of multiple buffers in a processor|
DB Papworth, AF Glew, GJ Hinton, RP Colwell, MA Fetterman, SR Gupta, ...
US Patent 5,778,245, 1998
|Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear …|
D Orenstein, O Wechsler, M Mittal, AF Glew, LM Mennemeier, AD Peleg, ...
US Patent 5,835,748, 1998