| RevLib: An online resource for reversible functions and reversible circuits R Wille, D Große, L Teuber, GW Dueck, R Drechsler 38th International Symposium on Multiple Valued Logic (ismvl 2008), 220-225, 2008 | 337 | 2008 |
| BDD-based synthesis of reversible logic for large functions R Wille, R Drechsler Proceedings of the 46th Annual Design Automation Conference, 270-275, 2009 | 326 | 2009 |
| Exact multiple-control toffoli network synthesis with SAT techniques D Große, R Wille, GW Dueck, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 229* | 2009 |
| Verifying UML/OCL models using Boolean satisfiability M Soeken, R Wille, M Kuhlmann, M Gogolla, R Drechsler Proceedings of the Conference on Design, Automation and Test in Europe, 1341 …, 2010 | 155 | 2010 |
| Elementary quantum gate realizations for multiple-control Toffoli gates DM Miller, R Wille, Z Sasanian 2011 41st IEEE International Symposium on Multiple-Valued Logic, 288-293, 2011 | 133 | 2011 |
| Synthesis of quantum circuits for linear nearest neighbor architectures M Saeedi, R Wille, R Drechsler Quantum Information Processing 10 (3), 355-377, 2011 | 131 | 2011 |
| Synthesis of reversible circuits with minimal lines for large functions M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler 17th Asia and South Pacific Design Automation Conference, 85-92, 2012 | 105 | 2012 |
| RevKit: A Toolkit for Reversible Circuit Design. M Soeken, S Frehse, R Wille, R Drechsler J. Multiple Valued Log. Soft Comput. 18 (1), 55-65, 2012 | 105 | 2012 |
| Towards a design flow for reversible logic R Wille, R Drechsler Springer Science & Business Media, 2010 | 105 | 2010 |
| An efficient methodology for mapping quantum circuits to the IBM QX architectures A Zulehner, A Paler, R Wille IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 94 | 2018 |
| Assisted behavior driven development using natural language processing M Soeken, R Wille, R Drechsler International Conference on Modelling Techniques and Tools for Computer …, 2012 | 82 | 2012 |
| Equivalence checking of reversible circuits R Wille, D Große, DM Miller, R Drechsler 2009 39th International Symposium on Multiple-Valued Logic, 324-330, 2009 | 81 | 2009 |
| Reducing reversible circuit cost by adding lines DM Miller, R Wille, R Drechsler 2010 40th IEEE International Symposium on Multiple-Valued Logic, 217-222, 2010 | 74 | 2010 |
| RevKit: An open source toolkit for the design of reversible circuits M Soeken, S Frehse, R Wille, R Drechsler International Workshop on Reversible Computation, 64-76, 2011 | 68 | 2011 |
| Verifying dynamic aspects of UML models M Soeken, R Wille, R Drechsler 2011 Design, Automation & Test in Europe, 1-6, 2011 | 68 | 2011 |
| SyReC: A programming language for synthesis of reversible circuits R Wille, S Offermann, R Drechsler 2010 Forum on Specification & Design Languages (FDL 2010), 1-6, 2010 | 63 | 2010 |
| Automatic design of low-power encoders using reversible circuit synthesis R Wille, R Drechsler, C Osewold, A Garcia-Ortiz 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 62 | 2012 |
| Reducing the number of lines in reversible circuits R Wille, M Soeken, R Drechsler Design Automation Conference, 647-652, 2010 | 61 | 2010 |
| Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits R Wille, O Keszocze, M Walter, P Rohrs, A Chattopadhyay, R Drechsler 2016 21st Asia and South Pacific design automation conference (ASP-DAC), 292-297, 2016 | 59 | 2016 |
| Exact reordering of circuit lines for nearest neighbor quantum architectures R Wille, A Lye, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 59 | 2014 |
