Optimum energy efficient error control techniques in wireless systems: a survey P Salija, B Yamuna journal of Communications Technology and Electronics 60, 1257-1263, 2015 | 18 | 2015 |
Support vector machine based decoding algorithm for BCH codes V Sudharsan, B Yamuna Journal of telecommunications and information technology, 108-112, 2016 | 10 | 2016 |
A reliability level list based SDD algorithm for binary cyclic block codes B Yamuna, TR Padmanabhan International Journal of Computers Communications & Control 7 (2), 388-395, 2012 | 9 | 2012 |
Effect of hardware trojans on the performance of a coded communication system AR Aravind, SR Kesavaraman, K Balasubramanian, B Yamuna, ... 2018 IEEE International Conference on Consumer Electronics (ICCE), 1-6, 2018 | 8 | 2018 |
Modified Min Sum Decoding Algorithm for Low Density Parity Check Codes J Shrinidhi, PS Krishna, B Yamuna, K Pargunarajan Procedia Computer Science 171, 2128-2136, 2020 | 7 | 2020 |
FPGA implementation of an area efficient matrix code with encoder reuse method J Athira, B Yamuna 2018 International Conference on Communication and Signal Processing (ICCSP …, 2018 | 7 | 2018 |
A novel reliability-based high performance decoding algorithm for short block length turbo codes P Salija, B Yamuna, TR Padmanabhan, D Mishra International Journal of Ad Hoc and Ubiquitous Computing 33 (3), 155-167, 2020 | 6 | 2020 |
Low power and area efficient max-log-MAP decoder K Eluri, B Yamuna, K Balasubramanian, D Mishra 2018 International Conference on Advances in Computing, Communications and …, 2018 | 6 | 2018 |
An efficient early iteration termination for turbo decoder P Salija, B Yamuna Journal of Telecommunications and Information Technology, 2016 | 6 | 2016 |
A minimal search soft decision list decoding algorithm for Reed-Solomon codes B Yamuna, TR Padmanabhan International Journal of Information and Communication Technology 6 (1), 71-85, 2014 | 6 | 2014 |
Performance analysis of reliability-based decoding algorithm for short block length turbo codes P Salija, B Yamuna, TR Padmanabhan, D Mishra IETE Journal of Research 68 (3), 1736-1747, 2022 | 5 | 2022 |
A low power hard decision decoder for bch codes P Garlapati, B Yamuna, K Balasubramanian 2021 International Conference on Advances in Computing and Communications …, 2021 | 5 | 2021 |
FPGA based implementation of a floating point multiplier and its hardware trojan models S Nikhila, B Yamuna, K Balasubramanian, D Mishra 2019 IEEE 16th India council international conference (INDICON), 1-4, 2019 | 5 | 2019 |
Design and Implementation of Interleaver in GNU Radio for short block length Turbo codes M Sreedevi, B Yamuna, P Salija 2019 9th International Conference on Advances in Computing and Communication …, 2019 | 5 | 2019 |
Implementation of turbo code with early iteration termination in GNU radio P Salija, B Yamuna Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 9 …, 2017 | 5 | 2017 |
Performance enhanced iterative soft-input soft-output decoding algorithms for block turbo codes V Sudharsan, V Karthik, JS Vaishnavi, S Abirami, B Yamuna Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 8 …, 2016 | 5 | 2016 |
Design of a low power and high-speed Viterbi decoder using T-algorithm with normalization R Surya, K Balasubramanian, B Yamuna 2021 international conference on advances in computing and communications …, 2021 | 4 | 2021 |
Design and analysis of a secure coded communication system using chaotic encryption and turbo product code decoder S Khavya, K Balasubramanian, B Yamuna, D Mishra Advances in Computing and Network Communications: Proceedings of CoCoNet …, 2021 | 4 | 2021 |
Hardware design of a turbo product code decoder GC Nair, B Yamuna, K Balasubramanian, D Mishra Proceedings of International Conference on Communication, Circuits, and …, 2021 | 4 | 2021 |
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study V Kakkara, K Balasubramanian, B Yamuna, D Mishra, ... PeerJ Computer Science 6, e250, 2020 | 4 | 2020 |