Dr.B. Yamuna
Dr.B. Yamuna
Verified email at cb.amrita.edu
Title
Cited by
Cited by
Year
Optimum energy efficient error control techniques in wireless systems: A survey
P Salija, B Yamuna
Journal of Communications Technology and Electronics 60 (11), 1257-1263, 2015
152015
A reliability level list based SDD algorithm for binary cyclic block codes
B Yamuna, TR Padmanabhan
International Journal of Computers Communications & Control 7 (2), 388-395, 2014
92014
Effect of hardware trojans on the performance of a coded communication system
AR Aravind, SR Kesavaraman, K Balasubramanian, B Yamuna, ...
2018 IEEE International Conference on Consumer Electronics (ICCE), 1-6, 2018
62018
A minimal search soft decision list decoding algorithm for Reed-Solomon codes
B Yamuna, TR Padmanabhan
International Journal of Information and Communication Technology 6 (1), 71-85, 2014
52014
Support vector machine based decoding algorithm for BCH codes
V Sudharsan, B Yamuna
Journal of Telecommunications and Information Technology, 2016
42016
An efficient early iteration termination for turbo decoder
P Salija, B Yamuna
Journal of Telecommunications and Information Technology, 2016
42016
Hardware implementation of CNN
S Veni, B Yamuna
Proceedings of 2005 International Conference on Intelligent Sensing and …, 2005
42005
Implementation of turbo code with early iteration termination in gnu radio
P Salija, B Yamuna
Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 9 …, 2017
32017
Performance enhanced iterative soft-input soft-output decoding algorithms for block turbo codes
V Sudharsan, V Karthik, JS Vaishnavi, S Abirami, B Yamuna
Journal of Telecommunication, Electronic and Computer Engineering (JTEC) 8 …, 2016
32016
Some investigations on a class of reliability based soft decision decoding algorithms for block codes
B Yamuna
Coimbatore, 2013
32013
A novel reliability-based high performance decoding algorithm for short block length turbo codes
P Salija, B Yamuna, TR Padmanabhan, D Mishra
International Journal of Ad Hoc and Ubiquitous Computing 33 (3), 155-167, 2020
12020
FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder
A Ambat, K Balasubramanian, B Yamuna, D Mishra
2018 International Conference on Advances in Computing, Communications and …, 2018
12018
Low power and area efficient max-log-MAP decoder
K Eluri, B Yamuna, K Balasubramanian, D Mishra
2018 International Conference on Advances in Computing, Communications and …, 2018
12018
FPGA Implementation of an Area Efficient Matrix Code with Encoder Reuse Method
J Athira, B Yamuna
2018 International Conference on Communication and Signal Processing (ICCSP …, 2018
12018
Implementation Of Low Complex SOVA In GNU Radio
P Durga, B Yamuna, P Salija
Procedia computer science 143, 876-885, 2018
12018
A low complex turbo decoding algorithm with early iteration termination
CR Seethal, B Yamuna
2017 International Conference on Advances in Computing, Communications and …, 2017
12017
Reliability level list-based decoding of multilevel modulated block codes
B Yamuna, TR Padmanabhan
International Journal of Information and Communication Technology, 2016
12016
Reliability level list based direct target codeword identification algorithm for binary BCH codes'
B Yamuna, TR Padmanabhan
WSEAS Transactions on Communications 12 (6), 287-299, 2013
12013
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study
V Kakkara, K Balasubramanian, B Yamuna, D Mishra, ...
PeerJ Computer Science 6, e250, 2020
2020
Modified Min Sum Decoding Algorithm for Low Density Parity Check Codes
J Shrinidhi, PS Krishna, B Yamuna, K Pargunarajan
Procedia Computer Science 171, 2128-2136, 2020
2020
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Articles 1–20