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Sri Parameswaran
Sri Parameswaran
School of Computer Science and Engineering, The University of New South Wales
Verified email at cse.unsw.edu.au
Title
Cited by
Cited by
Year
NoCGEN: A template based reuse methodology for networks on chip architecture
J Chan, S Parameswaran
17th International Conference on VLSI Design. Proceedings., 717-720, 2004
1082004
Design methodology for pipelined heterogeneous multiprocessor system
SL Shee, S Parameswaran
Proceedings of the 44th annual Design Automation Conference, 811-816, 2007
852007
RIJID: Random code injection to mask power analysis based side channel attacks
JA Ambrose, RG Ragel, S Parameswaran
Proceedings of the 44th annual Design Automation Conference, 489-492, 2007
832007
Finding optimal l1 cache configuration for embedded systems
A Janapsatya, A Ignjatović, S Parameswaran
Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006
832006
IMPRES: integrated monitoring for processor reliability and security
RG Ragel, S Parameswaran
2006 43rd ACM/IEEE Design Automation Conference, 502-505, 2006
802006
darknoc: Designing energy-efficient network-on-chip with multi-vt cells for dark silicon
H Bokhari, H Javaid, M Shafique, J Henkel, S Parameswaran
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
742014
Designing embedded processors: a low power perspective
J Henkel, S Parameswaran
Springer, 2007
722007
Embedded systems security—an overview
S Parameswaran, T Wolf
Design Automation for Embedded Systems 12 (3), 173-183, 2008
712008
A novel instruction scratchpad memory optimization method based on concomitance metric
A Janapsatya, A Ignjatović, S Parameswaran
Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006
712006
Dark silicon as a challenge for hardware/software co-design: Invited special session paper
M Shafique, S Garg, T Mitra, S Parameswaran, J Henkel
Proceedings of the 2014 International Conference on Hardware/Software …, 2014
652014
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
J Chan, S Parameswaran
2008 Asia and South Pacific Design Automation Conference, 265-270, 2008
632008
MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm
JA Ambrose, S Parameswaran, A Ignjatovic
2008 IEEE/ACM International Conference on Computer-Aided Design, 678-684, 2008
582008
Minimally biased multipliers for approximate integer and floating-point multiplication
H Saadat, H Bokhari, S Parameswaran
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
572018
Hardware/software managed scratchpad memory for embedded system
A Janapsatya, S Parameswaran, A Ignjatovic
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
572004
Inside: Instruction selection/identification & design exploration for extensible processors
N Cheung, S Parameswaran, J Henkel
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
572003
NoCEE: energy macro-model extraction methodology for network on chip routers
J Chan, S Parameswaran
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
552005
Rapid configuration and instruction selection for an ASIP: a case study
N Cheung, J Henkel, S Parameswaran
2003 Design, Automation and Test in Europe Conference and Exhibition, 802-807, 2003
532003
Configurable multimode embedded floating-point units for FPGAs
YJ Chong, S Parameswaran
IEEE transactions on very large scale integration (VLSI) systems 19 (11 …, 2010
492010
Heterogeneous multiprocessor implementations for jpeg: a case study
SL Shee, A Erdos, S Parameswaran
Proceedings of the 4th international conference on Hardware/software …, 2006
482006
A design flow for application specific heterogeneous pipelined multiprocessor systems
H Javaid, S Parameswaran
Proceedings of the 46th Annual Design Automation Conference, 250-253, 2009
472009
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