| Multi retention level STT-RAM cache designs with a dynamic refresh scheme Z Sun, X Bi, H Li, WF Wong, ZL Ong, X Zhu, W Wu proceedings of the 44th annual IEEE/ACM international symposium on …, 2011 | 294 | 2011 |
| Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches X Bi, Z Sun, H Li, W Wu Proceedings of the International Conference on Computer-Aided Design, 88-94, 2012 | 87 | 2012 |
| Unleashing the potential of MLC STT-RAM caches X Bi, M Mao, D Wang, H Li 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 429-436, 2013 | 60 | 2013 |
| STT-RAM cache hierarchy with multiretention MTJ designs Z Sun, X Bi, H Li, WF Wong, X Zhu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6 …, 2013 | 58 | 2013 |
| Process variation aware data management for STT-RAM cache design Z Sun, X Bi, H Li Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 57 | 2012 |
| STT-RAM cell design considering CMOS and MTJ temperature dependence X Bi, H Li, X Wang IEEE Transactions on Magnetics 48 (11), 3821-3824, 2012 | 43 | 2012 |
| Array organization and data management exploration in racetrack memory Z Sun, X Bi, W Wu, S Yoo, H Li IEEE Transactions on Computers 65 (4), 1041-1054, 2014 | 36 | 2014 |
| Design exploration of racetrack lower-level caches Z Sun, X Bi, AK Jones, H Li Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 34 | 2014 |
| Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration J Wang, P Roy, WF Wong, X Bi, H Li 2014 IEEE 32nd International Conference on Computer Design (ICCD), 133-138, 2014 | 30 | 2014 |
| An efficient STT-RAM-based register file in GPU architectures X Liu, M Mao, X Bi, H Li, Y Chen The 20th Asia and South Pacific Design Automation Conference, 490-495, 2015 | 25 | 2015 |
| Spintronic memristor based temperature sensor design with CMOS current reference X Bi, C Zhang, H Li, Y Chen, RE Pino 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 23 | 2012 |
| Analysis and optimization of thermal effect on STT-RAM Based 3-D stacked cache design X Bi, H Li, JJ Kim 2012 IEEE Computer Society Annual Symposium on VLSI, 374-379, 2012 | 19 | 2012 |
| Cross-layer optimization for multilevel cell STT-RAM caches X Bi, M Mao, D Wang, HH Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (6 …, 2017 | 18 | 2017 |
| STT-RAM designs supporting dual-port accesses X Bi, MA Weldon, H Li 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 853-858, 2013 | 17 | 2013 |
| Exploring applications of STT-RAM in GPU architectures X Liu, M Mao, X Bi, H Li, Y Chen IEEE Transactions on Circuits and Systems I: Regular Papers 68 (1), 238-249, 2020 | 9 | 2020 |
| Magnetic-assisted nondestructive self-reference sensing method for spin-transfer torque random access memory Y Chen, E Eken, H Li, W Wen, X Bi US Patent 9,627,024, 2017 | 5 | 2017 |
| Design and implementation of a 4kb stt-mram with innovative 200nm nano-ring shaped mtj Z Li, X Bi, HH Li, Y Chen, J Qin, P Guo, W Kong, W Zhan, X Han, H Zhang, ... Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 3 | 2016 |
| A pseudo-weighted sensing scheme for memristor based cross-point memory Z Chen, L Zhang, X Bi, H Li 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2013 | 3 | 2013 |
| Design and FPGA implementation of 3DES against Power Analysis Attacks for IC bankcard X Bi, L Wu, G Bai 2009 IEEE 8th International Conference on ASIC, 159-162, 2009 | 2 | 2009 |
| Circuit and architecture co-design of stt-ram for high performance and low energy X Bi University of Pittsburgh, 2017 | 1 | 2017 |
Hai LiMarie Foote Reel E'46 Distinguished Professor of ECE Dept, Duke Univ.Verified email at duke.edu
