| A structured approach to post-silicon validation and debug using symbolic quick error detection D Lin, E Singh, C Barrett, S Mitra 2015 IEEE International Test Conference (ITC), 1-10, 2015 | 35 | 2015 |
| Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs E Singh 29th VLSI Test Symposium, 32-37, 2011 | 29 | 2011 |
| Logic bug detection and localization using symbolic quick error detection E Singh, D Lin, C Barrett, S Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018 | 26 | 2018 |
| Impact of radial defect clustering on 3D stacked IC yield from wafer to wafer stacking E Singh 2012 IEEE International Test Conference, 1-7, 2012 | 19 | 2012 |
| Gap-free Processor Verification by S2QED and Property Generation K Devarajegowda, MR Fadiheh, E Singh, C Barrett, S Mitra, W Ecker, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 526-531, 2020 | 17 | 2020 |
| E-QED: electrical bug localization during post-silicon validation enabled by quick error detection and formal methods E Singh, C Barrett, S Mitra International Conference on Computer Aided Verification, 104-125, 2017 | 16 | 2017 |
| Symbolic qed pre-silicon verification for automotive microcontroller cores: Industrial case study E Singh, K Devarajegowda, S Simon, R Schnieder, K Ganesan, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 13 | 2019 |
| A-QED verification of hardware accelerators E Singh, F Lonsing, S Chattopadhyay, M Strange, P Wei, X Zhang, Y Zhou, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 10 | 2020 |
| Analytical modeling of 3D stacked IC yield from wafer to wafer stacking with radial defect clustering E Singh 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 10 | 2014 |
| Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED F Lonsing, K Ganesan, M Mann, SS Nuthakki, E Singh, M Srouji, Y Yang, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 8 | 2019 |
| Post-silicon validation and debug using symbolic quick error detection S Mitra, C Barrett, D Lin, E Singh US Patent 10,528,448, 2020 | 7 | 2020 |
| Effective pre-silicon verification of processor cores by breaking the bounds of symbolic quick error detection K Ganesan, F Lonsing, SS Nuthakki, E Singh, MR Fadiheh, W Kunz, ... arXiv preprint arXiv:2106.10392, 2021 | 4 | 2021 |
| Wafer ordering heuristic for iterative wafer matching in w2w 3d-sics with diverse die yields E Singh 3D-Test First IEEE International Workshop on Testing Three-Dimensional …, 2010 | 4 | 2010 |
| Symbolic quick error detection for pre-silicon and post-silicon validation: Frequently asked questions E Singh, D Lin, C Barrett, S Mitra IEEE Design & Test 33 (6), 55-62, 2016 | 3 | 2016 |
| Learned Formal Proof Strengthening for Efficient Hardware Verification M Kang, A Nova, E Singh, GS Bathini, Y Viktorov, J Wawrzynek | | 2023 |
| LFPS: Learned Formal Proof Strengthening for Efficient Hardware Verification M Kang, A Nova, E Singh, GS Bathini, Y Viktorov 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | | 2023 |
| Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking E Singh 2014 IEEE 32nd VLSI Test Symposium (VTS), 1-6, 2014 | | 2014 |
| Tutorial T2E: Pre-Silicon Verification and Post-Silicon Validation: Dramatic Improvements through Disruptive Innovations S Mitra, SS Nuthakki, E Singh | | |
| ITC 2006 Most Significant Paper Award E Singh, C Barrett, S Mitra | | |
