Aditya Japa
Aditya Japa
Ph.D. scholar, ECE, IIIT NAYA RAIPUR
Verified email at iiitnr.edu.in
Title
Cited by
Cited by
Year
Reliability Enhancement of a Steep Slope Tunnel Transistor based Ring Oscillator Designs with Circuit Interaction
RV Aditya J, Harshita V
IET Circuits, Devices & Systems, 8, 2016
16*2016
Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm
H Vallabhaneni., A Japa., S Sadulla, KS Rama, V Ramesh
Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on, 1-5, 2014
142014
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities
RV Aditya Japa , T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa ...
IEEE International Symposium on Circuits and Systems (ISCAS), 2018, 2018
72018
Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks
A Japa, MK Majumder, SK Sahoo, R Vaddi
IET Circuits, Devices & Systems 13 (5), 689-695, 2019
52019
Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage
A Japa, MK Majumder, SK Sahoo, R Vaddi
Journal of Circuit Theory and Applications, Wiely, 2020
42020
Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator
A Japa, M Kumar Majumder, SK Sahoo, R Vaddi
IET Circuits, Devices & Systems 14 (5), 640-647, 2020
32020
Exploiting the steep subthreshold slope characteristics of tunnel transistors for wide tuning range voltage controlled ring oscillator (VCRO) design at scaled supply voltages …
J Aditya, S Sadulla, R Vaddi
2016 3rd International Conference on Emerging Electronics (ICEE), 1-2, 2016
32016
Tunneling field effect transistors for energy efficient logic, sensor interface and 3D IC circuits for IoT platforms
J Aditya, T Nagateja, R Vaddi
2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017
22017
Exploiting characteristics of steep slope tunnel transistors towards energy efficient and reliable buffer designs for IoT SoCs
J Aditya, V Harshita, R Vaddi
International Symposium on VLSI Design and Test, 259-269, 2017
12017
Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap
A Japa, MK Majumder, SK Sahoo, R Vaddi, BK Kaushik
IEEE Circuits and Systems Magazine 21 (3), 4-30, 2021
2021
Emerging Tunnel FET and Spintronics based Hardware Secure Circuit Design with Ultra-low Energy Consumption
A Japa, SK Sahoo, R Vaddi, MK Majumder
2021
Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things
J Aditya, M Manoj Kumar, S Subhendu K., V Ramesh
Journal of Circuit Theory and Applications, Wiely, 2021
2021
Introduction to Microelectronics to Nanoelectronics: Design and Technology
MK Majumder, VR Kumbhare, A Japa, BK Kaushik
CRC Press, 2020
2020
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET
A Japa, Y Palagani, V Gonuguntla, MK Majumder, SK Sahoo, JR Choi, ...
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
2020
Tunneling field effect transistors for energy efficient digital, RF and power management circuit designs enabling IoT edge computing platforms
J Aditya, T Nagateja, R Vaddi
VLSI and Post-CMOS Electronics 1, 2019
2019
Circuits
A Japa, MK Majumder, SK Sahoo, R Vaddi, BK Kaushik
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Articles 1–16