Follow
Prithviraj Pachal
Prithviraj Pachal
RnD Device Engineer, Micron Technology
Verified email at ufl.edu
Title
Cited by
Cited by
Year
Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V VDD Digital Logic Circuits
S Guha, P Pachal
IEEE Transactions on Nanotechnology 20, 576-583, 2021
202021
Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance
S Guha, P Pachal, S Ghosh, SK Sarkar
Superlattices and Microstructures 146, 106657, 2020
132020
Performance analysis of gas sensing device and corresponding IoT framework in mines
S Nath, A Dey, P Pachal, JK Sing, SK Sarkar
Microsystem Technologies 27, 3977-3985, 2021
122021
Nano Structured Gas Sensing Device and Its Application in Underground Mines
S Nath, A Dey, P Pachal, SR Chowdhury, JK Sing, SK Sarkar
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 445-449, 2018
72018
Double gate pnpn TFET with hetero oxide dielectric and high-k spacer engineering
S Ghosh, P Pachal, R Kumar, S Kundu, J Ghosh, SK Sarkar
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 1-5, 2020
32020
Design and Analog/RF Performance Analysis of a Novel Symmetric Raised-Channel SiGe Heterojunction Tunnel Field-Effect Transistor (TFET
S Guha, P Pachal
Silicon, 2020
32020
Performance Analysis of Underlap Double Gate Oxide Stacked Junctionless MOSFET for Analog and RF Applications
A Bhattacharyya, P Pachal, A Pradhan, M Chanda, D De
2019 TEQIP III Sponsored International Conference on Microwave Integrated …, 2019
12019
A computational study of the impact of voids on the percolation electronic conductivity of nanowire networks
G Cheng, P Pachal, D Gorle, A Ural
APS March Meeting Abstracts 2023, EE07. 001, 2023
2023
Exploring the Feasibility of Implementing Negative-Capacitance Tunnel-FET (NC-TFET) in Low-Power Digital Circuits
S Guha, P Pachal
2022 IEEE VLSI Device Circuit and System (VLSI DCS), 1-4, 2022
2022
Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET
S Ghosh, S Kundu, S Guha, J Ghosh, P Pachal, SK Sarkar
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 427-431, 2020
2020
Deepan Nagarajan 435 Dhana Lakshmi M 208 Digvijay Pandey 487 Dinesh Kumar 348, 396
M Divya Shree, E Supraja, G Narayanan, G Ravi, G Shiny, GT Raja, ...
The system can't perform the operation now. Try again later.
Articles 1–11