Deleep R. Nair
Deleep R. Nair
Professor, Department of Electrical Engg, IIT Madras
Verified email at - Homepage
Cited by
Cited by
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ...
2008 Symposium on VLSI Technology, 88-89, 2008
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ...
2011 IEEE International Electron Devices Meeting (IEDM), 28.1.1 - 28.1.4, 2011
32nm general purpose bulk CMOS technology for high performance applications at low voltage
F Arnaud, J Liu, YM Lee, KY Lim, S Kohler, J Chen, BK Moon, CW Lai, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Scaling of 32nm low power SRAM with high-K metal gate
HS Yang, R Wong, R Hasumi, Y Gao, NS Kim, DH Lee, S Badrudduza, ...
Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 1-4, 2008
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
F Arnaud, A Thean, M Eller, M Lipinski, YW Teh, M Ostermayr, K Kang, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Asymmetric channel MOSFET
X Chen, J Deng, W Li, DR Nair, JE Park, D Tekleab, X Yuan, NS Kim
US Patent 8,237,197, 2012
Method of manufacturing a body-contacted SOI FINFET
N Kanike, DR Nair
US Patent 8,993,402, 2015
Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters
DR Nair, S Mahapatra, S Shukuri, JD Bude
IEEE Transactions on Electron Devices 51 (5), 701-707, 2004
Piezoelectric-on-Silicon Array Resonators With Asymmetric Phononic Crystal Tethering
U Rawat, DR Nair, A DasGupta
Journal of Microelectromechanical Systems 26 (4), 773-781, 2017
Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET
VA Tiwari, D Jaeger, A Scholze, DR Nair
IEEE Transactions on Electron Devices, 61 (5), 1270 - 1277, 2014
Compact Modeling of Proximity Effect in High- Tapered Spiral Inductors
J Sathyasree, V Vanukuru, D Nair, A Chakravorty
IEEE Electron Device Letters 39 (4), 588-590, 2018
A Scalable, Broadband, and Physics-Based Model for On-Chip Rectangular Spiral Inductors
SS Jayaraman, V Vanukuru, D Nair, A Chakravorty
IEEE Transactions on Magnetics 55 (9), 1-6, 2019
Study of the Effect of Surface Roughness on the Performance of RF MEMS Capacitive Switches Through 3-D Geometric Modeling
S Gopalakrishnan, A Dasgupta, DR Nair
IEEE Journal of the Electron Devices Society 4 (6), 451-458, 2016
Novel RF MEMS capacitive switches with design flexibility for multi-frequency operation
S Gopalakrishnan, A DasGupta, DR Nair
Journal of Micromechanics and Microengineering 27 (9), 095013, 2017
Realization of preferential (100) oriented AlN thin films on Mo coated Si substrate using reactive RF magnetron sputtering
A Das, M Rath, DR Nair, MSR Rao, A DasGupta
Applied Surface Science 550, 149308, 2021
Oxygen scavenging spacer for a gate electrode
MP Chudzik, DR Nair, V Narayanan, CJ Radens, JM Shah
US Patent 9,059,211, 2015
Design, fabrication and characterization of RF MEMS shunt switch for wideband operation of 3 GHz to 30 GHz
A Swarnkar, A DasGupta, DR Nair
Journal of Micromechanics and Microengineering 29 (11), 115009, 2019
CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters
NR Mohapatra, DR Nair, S Mahapatra, V Ramgopal Rao, S Shukuri, ...
Electron Devices, IEEE Transactions on 50 (10), 2104-2111, 2003
A Substrate Model for On-Chip Tapered Spiral Inductors With Forward and Reverse Excitations
J Sathyasree, V Vanukuru, DR Nair, A Chakravorty
IEEE Transactions on Electron Devices 66 (1), 802-805, 2018
New layout dependency in high-k/Metal Gate MOSFETs
M Hamaguchi, D Nair, D Jaeger, H Nishimura, W Li, MH Na, C Bernicot, ...
2011 IEEE International Electron Devices Meeting (IEDM), 25.6.1 - 25.6.4, 2011
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